Coded data generation or conversion – Digital code to digital code converters – Programmable structure
Reexamination Certificate
2003-02-10
2004-09-07
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Programmable structure
C365S230010
Reexamination Certificate
active
06788228
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a device for addressing an arbitrary element from a set of N≦2
K
regular elements or alternatively an element from a set of R<N redundant elements depending on the binary values of the address bits of a K-bit input address. The address device has a 1-out-of-N decoder, which has K address inputs for receiving the address bits and N outputs for connection to the N regular elements. The device further has R bypass circuits, each of which is assigned to precisely one redundant element. The bypass circuits each have a sensitization circuit for setting the relevant bypass circuit into an active state, a reference bit transmitter for supplying K reference bits which are individually assigned to the K address bits and whose values are programmable by selective destruction or preservation of conductive links or by selective introduction of conducting links, a comparison device which derives K comparison bits from the reference bits and compares them with the respectively assigned address bits and supplies a hit information item if the address bits correspond to a bit combination which is unambiguously related to the bit combination of the comparison bits, and a control circuit, which, upon the appearance of the hit information item, supplies a selection signal which switches off the 1 out-of-N decoder and addresses the assigned redundant element if the relevant bypass circuit is set into the active state. A preferred, but not exclusive, area of application for the invention is the addressing of rows or columns of a memory matrix.
In assemblies that contain a multiplicity of selectively addressable elements and a corresponding addressing device, the functional test carried out after production may reveal that one or more of the elements are defective. Since the direct repair of a defective element is too complex or even impossible in many cases, at least one additional “redundant” element is provided besides the required number of regular elements as early as during the production of the assembly, which element can serve, as required, as a replacement for a defective element. The number R of redundant elements to be provided is usually less than the number N of regular elements and is dimensioned taking account of the maximum expected defect frequency. All of the redundant elements present are, of course, likewise subjected to a functional test.
The addressing of the elements is typically effected digitally by a multi-bit address using a 1-out-of-N decoder contained in the addressing device, where N is the number of regular elements. If it is desired to fully utilize the available address array, an integer power of 2 is chosen for the number N, that is to say N=2
K
, where K is the number of bits of the input address for the 1-out-of-N decoder.
In order to replace each defective regular element in a system by a respective defect-free specimen of the R redundant elements, manipulations are performed at the addressing device after the test in order to ensure that, upon the appearance of the input address for a defective regular element, the 1-out-of-N decoder is switched off and the addressing is “bypassed” to a respectively selected element of the R redundant elements. For this purpose, the addressing device is additionally provided with R bypass circuits, each of which leads to one of the redundant elements and contains a programmable reference bit transmitter and also a comparison and control logic. Each reference bit transmitter contains a device for providing K bits that can be arbitrarily programmed after the production of the system in order to prescribe a K-bit comparison address. The assigned bypass circuit compares the address with the input address. In the event of correspondence, it switches off the 1-out-of-N decoder and addresses the redundant element assigned to it.
Once the functional test of the assembly has shown which regular and redundant elements are defective, the addresses of the defective regular elements are programmed into the reference bit transmitters. For this purpose, it is possible, of course, to select the reference bit transmitters only of those bypass circuits which lead to defect-free redundant elements. After the programming, it is ensured that when an input address corresponding to a defective element is applied, the 1-out-of-N decoder is inactive, and that the defect-free redundant element selected for this address is addressed instead.
It is generally customary for the reference bit transmitters to be configured in such a way that they can be programmed by so-called “fuse” technology. For this purpose, the K circuit nodes of each reference bit transmitter, at which the K bits of the comparison address are supplied, are connected to a first of the two logic potentials L or H, which represent the binary values “0” and “1”, via a respective destructible conductive link. Moreover, each of the circuit nodes is connected to the respective other logic potential via a second branch. The configuration is dimensioned in such a way that the circuit node is pulled to the first logic potential in the case of an undestroyed link and is pulled to the other logic potential when the link is destroyed. The links are usually low-value resistors which can be selectively fused e.g. by a laser beam or applied over-voltage (so-called fusible links or “fuses”).
Each reference bit transmitter of the type described above can thus be programmed to an arbitrary K-bit address by destruction or preservation of selected specimens of its links in order to ensure that the addressing of the regular element which is normally assigned to the address is bypassed to the redundant element which is assigned to the relevant reference bit transmitter. Even if none of the links in a reference bit transmitter is destroyed, there is a programming to a K-bit address. This would be e.g. the zero address if all the links lead to that logic potential which represents the binary value “0”. Thus, a programming state that would not correspond to some of the N input addresses is not possible for a reference bit transmitter.
The above-mentioned functional test may reveal that no or not all the redundant elements are actually required as a replacement (because the number of defective regular elements is less than the number of redundant elements present) or that certain redundant elements are not permitted to be used as a replacement (because they are defective themselves). In these cases, the redundant elements that are not to be used must be prevented from being addressed in an undesirable manner via the assigned bypass circuits. For this reason, a separate sensitization circuit must be provided for each bypass circuit in order that the bypass circuit is put into a active state only when a decision has been taken on account of the functional test that the assigned redundant element is actually to be used as a replacement element.
In the prior art, the above-mentioned sensitization circuits are realized in each case by an addition, superordinate fusible link (“master fuse”) in each bypass circuit. Each of these additional links can be destroyed selectively, in the same way as the other links in the reference bit transmitters. Each additional link is typically disposed in such a way that the relevant bypass circuit can operate only when the additional link is destroyed.
The use of the above-mentioned additional links in accordance with the prior art has disadvantages. This is because destructible links require much space and cannot be miniaturized to the same extent as other circuit components. On the one hand, such a link, particularly if, as is customary, it is formed by a fusible low-value resistor, already takes up a relatively large area for itself. On the other hand, it is necessary to comply with a relatively large distance between the fusible links and also from other circuit sections in order that a targeted destructive access is readily possible without influencing adjacent components. These space require
Fischer Helmut
Morgan Alan
Greenberg Laurence A.
Infineon - Technologies AG
Jean-Pierre Peguy
Locher Ralph E.
Stemer Werner H.
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