Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2008-04-22
2010-11-30
Ellis, Kevin L (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S103000, C711S148000, C711S150000
Reexamination Certificate
active
07844786
ABSTRACT:
Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be assigned an address through a set of discrete voltages. One, multiple, or all of the memory modules may be addressed with a single command, which may be an increment counter command, a write command, or a punch out bit field. The status of the memory modules may be determined by sampling a single signal that may be at a low, high, or intermediate voltage level.
REFERENCES:
patent: 4586147 (1986-04-01), Tadokoro
patent: 4631428 (1986-12-01), Grimes
patent: 4689740 (1987-08-01), Moelands et al.
patent: 5023813 (1991-06-01), Brown, III
patent: 5044790 (1991-09-01), Kawamura
patent: 5297269 (1994-03-01), Donaldson et al.
patent: 5479467 (1995-12-01), Katsumata
patent: 5689196 (1997-11-01), Schutte
patent: 6002846 (1999-12-01), Okamoto
patent: 6052547 (2000-04-01), Cuzzo et al.
patent: 6249838 (2001-06-01), Kon
patent: 6253277 (2001-06-01), Lakhani et al.
patent: 6307779 (2001-10-01), Roohparvar
patent: 6442076 (2002-08-01), Roohparvar
patent: 6641312 (2003-11-01), Chang et al.
patent: 6665092 (2003-12-01), Reed
patent: 6760274 (2004-07-01), Roohparvar
patent: 2002/0085433 (2002-07-01), Tomori et al.
patent: 2003/0011409 (2003-01-01), Altrichter et al.
patent: 2003/0043408 (2003-03-01), Fields et al.
patent: 2003/0133331 (2003-07-01), LaBerge
patent: 2004/0133794 (2004-07-01), Kocher et al.
patent: 2004/0178278 (2004-09-01), Fruhauf et al.
patent: 2005/0036620 (2005-02-01), Casden et al.
AN10216-01 Jean-Marc Irazabal, Steve Blozis, “12C Manual,” Application Note, Philips Semiconductors, pp. 1-51, (Mar. 24, 2003).
DS1961S “ikb Protected EEPROM iButton with SHA-1 Engine,” Dallas Semiconductor, www.maxim-ic.com, pp. 1-36 (date: unknown).
“The 12C-Bus Specification” Version 2.1, Philips Semiconductors, pp. 1-46, (Jan. 2000).
Booth James Ronald
Willett Bryan Scott
Bertram Ryan
Ellis Kevin L
Lexmark International Inc.
LandOfFree
Addressing and command protocols for non-volatile memories... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Addressing and command protocols for non-volatile memories..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Addressing and command protocols for non-volatile memories... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4167112