Addressing a cache

Computer graphics processing and selective visual display system – Computer graphics display memory system – Cache

Reexamination Certificate

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Details

C345S568000, C711S202000, C711S003000

Reexamination Certificate

active

06977657

ABSTRACT:
A data processing system has main memory and one or more caches. Data from main memory is cached while mitigating the effects of address pattern dependency. Main memory physical addresses are translated into main memory virtual address under the control of an operating system. The translation occurs on a page-by-page basis such that some of the virtual address bits are the same as some of the physical address bits. A portion of the address bits that are the same are selected and cache offset values are generated from the selected portion. Data is written to the cache at offset positions derived from the cache offset values.

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