Address watch breakpoints in a hardware synchronization range

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Details

C714S032000, C714S033000, C714S035000

Reexamination Certificate

active

10808739

ABSTRACT:
A method, apparatus, system, and signal-bearing medium that in an embodiment determine whether an instruction at which an address watch breakpoint occurs is within a hardware synchronization mechanism range in a program. If the determination is true, a special breakpoint is set following the hardware synchronization mechanism range, the address watch breakpoint is temporarily disabled, and the machine state is saved. When the program encounters the special breakpoint following the end of the hardware synchronization mechanism range, the saved machine state is presented. In this way, endless looping in programs protected by hardware synchronization mechanisms may be prevented.

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patent: 6823482 (2004-11-01), Ahrens et al.
patent: 2002/0112203 (2002-08-01), Andress et al.
patent: 2005/0160328 (2005-07-01), Lesartre et al.

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