Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1996-09-27
2001-02-06
Teska, Kevin J. (Department: 2763)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S056000
Reexamination Certificate
active
06185634
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a DMA controller which monitors the addresses involved in a DMA transfer, and generates a signal when a predetermined address is involved in the DMA transfer.
BACKGROUND OF THE INVENTION
Present computer systems include one or more main, or host, processors, each including associated memory for storing programs to be executed and data to be processed. Such systems also include one or more input/output (I/O) peripheral device controllers. The host processors, memory, and peripheral device controllers are all coupled together by a system bus. Such peripheral device controllers may include their own memory and a local processor to control the operation of the peripheral device controller and the peripheral devices to which it is attached. One type of peripheral device controller may be coupled to a plurality of mass storage devices, such a disk drives. A peripheral device controller for a disk drive system includes respective host adapters for coupling to the host processors, and one or more disk adapters, each coupled to one or more disk drives. These adapters are all coupled together via a local bus.
In some such computer systems it is absolutely necessary that data be stored in such a manner that it will not be lost in the event of a failure of a portion of the computer system. This is generally accomplished by providing redundant hardware and/or storing multiple copies of the data. For example, in a disk drive system, a host computer desiring to store data on the disk drives transfers a copy of that data from its memory to the disk drive controller. The disk drive controller stores in its local memory two copies of the data in two different places. Only when the two copies of the data have been made and their accuracy verified is the host processor notified that the data was successfully received by the disk drive system. The disk drive controller then transfers the data from the local memory to the disk drives in such a manner that it may be recovered, even if a disk drive should fail, for example using a RAID arrangement.
Both of these transfers of data are generally made under the control of direct memory access (DMA) controllers in a known manner. A DMA data transfer takes place independently of the program being executed by the processor (either host or local), and can occur at the full burst throughput rate of the host system bus. DMA transfers are generally initiated by providing the DMA controller with: (1) a starting address of the location in the host processor memory containing the data to be sent to the disk drive system (termed the source address); (2) either the amount of data to be transferred, or the ending address the data in the host processor memory (the end address); and (3) the I/O address of the disk drive controller to which it is desired to send the data (the destination address). The DMA controller then requests the host processor to grant it access to the system bus. When access is granted, the DMA controller enables a burst of data of a predetermined size to be transferred by accessing the host processor memory. More specifically, the DMA controller conditions the host memory to place data on the system bus, by placing a memory address on the system bus, conditioning the host memory to place data from the addressed location on the system bus, and simultaneously conditioning the disk drive system to store the data from the system bus in it's local memory. When this transfer is complete, the address is incremented, and the DMA cycle repeated until all the desired data has been transferred, all in a known manner.
If the block of data to be written is large, the transfer of the data from the host computer system to the disk drive controller, and the copying of that data within the disk drive controller can take a relatively long time, and the transfer of that data to the disk drives themselves does not start until the data has been completely and successfully received by the disk drive controller. However, it is possible that sufficient data is received to begin a transfer from the disk drive controller to the disk drives within a relatively short period of time. It is desirable to begin transfer of data from the memory in the disk drive controller to the disk drives as soon as there is sufficient data to do so to minimize the delay from the start of the data transfer from the host computer system until the data is safely written onto the disk drives.
BRIEF SUMMARY OF THE INVENTION
In accordance with principles of the present invention an address triggered DMA controller includes a DMA engine for controlling transfer of data between an external device and locations in a memory designated by respective addresses. Such a DMA controller also includes a DMA monitor for monitoring the respective addresses, and if one of the respective addresses matches a predetermined value, generating a signal to indicate a match.
An address triggered DMA controller according to the invention monitors the memory addresses of the data being transferred via DMA, and when the memory address matches a value, a match indicative signal is generated. In the above example, the predetermined address may be set to the size of a sector, or cluster, or other unitary block of data for the disk drive system. When the address corresponding to the end of such a block is accessed, a signal is generated, indicating that a block of data has been received by the disk drive controller and stored in the local memory. In response to that signal, the disk drives may be conditioned to initiate transfer of that block of data from the local memory to the disk drives themselves. In the meantime, the transfer of the data from the host processor to the disk drive controller may continue. The predetermined address may also be adjusted to indicate receipt of a second disk drive data block and the disk drives notified of the receipt of a second data block, and so on. In this manner, the latency between receipt of data to be stored on disk drives, and the transfer of that data to the disk drives may be minimized.
REFERENCES:
patent: 4599689 (1986-07-01), Berman
patent: 4864533 (1989-09-01), Hanada
patent: 4989135 (1991-01-01), Miki
patent: 5159671 (1992-10-01), Iwami
patent: 5179709 (1993-01-01), Bailey et al.
patent: 5214767 (1993-05-01), Wanner et al.
patent: 5239659 (1993-08-01), Rudeseal et al.
patent: 5333274 (1994-07-01), Amini et al.
patent: 5379381 (1995-01-01), Lamb
patent: 5485624 (1996-01-01), Steinmetz et al.
patent: 5537646 (1996-07-01), Buck et al.
patent: 5551006 (1996-08-01), Kulkarni
patent: 5572660 (1996-11-01), Jones
patent: 5590377 (1996-12-01), Smith
patent: 5623700 (1997-04-01), Parks et al.
patent: 5632016 (1997-05-01), Hoch et al.
patent: 5636188 (1997-06-01), Funahashi
patent: 5644784 (1997-07-01), Peek
patent: 5652915 (1997-07-01), Jeter et al.
patent: 5659777 (1997-08-01), Iwasaki et al.
patent: 5687392 (1997-11-01), Radko
patent: 5768557 (1998-06-01), Kulkarni
patent: 5835733 (1998-11-01), Walsh et al.
Caracappa David N.
EMC Corporation
Fitzgerald Leanne J.
Gunther John M.
Teska Kevin J.
LandOfFree
Address triggered DMA controller with an indicative signal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Address triggered DMA controller with an indicative signal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address triggered DMA controller with an indicative signal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2572409