Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1998-03-25
2001-04-17
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S206000, C712S229000
Reexamination Certificate
active
06219774
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of electronic data processing devices. More specifically, the invention relates to the operation of processors.
2. Background Information
As computer systems continue to evolve, it is desirable to develop more technologically advanced processors which use new instruction sets and/or new resources for supporting operating system type functions. For example, it has recently become desirable to develop processors which incorporate RISC based instruction sets and/or which utilize larger address spaces. At the same time, it is desirable to remain compatible with the existing base of software (including operating systems) developed for previous processors. The term architecture is used herein to refer to all or part of a computer system, and may include chips, circuits, and system programs.
One prior art architecture which attempted to deal with this limitation is implemented in the VAX-11. The VAX-11 incorporates a new instruction set and extends the PDP-11 architecture from using 16 addressing bits to using 32 addressing bits. The VAX-11 is capable of executing application programs written in either the new VAX-11 instruction set or the PDP-11 instruction set. However, the VAX-11 has several limitations. One such limitation is that the VAX-11 cannot execute an application program written with instructions from both instruction sets because it lacks the ability to share data generated by the different instruction sets. Thus, the VAX-11 does not provide the option of using the new instruction set where justified by performance advantages and using the existing software where justified by development cost considerations. As a result, software developers have the difficult choice of either incurring large development costs to develop an entirely new application program or forgoing the benefits offered by the new instruction set. Another limitation is that the VAX-11 provides one mechanism for supporting operating system type functionality (e.g., only one memory management mechanism and only one event handling mechanism) and can only accept an operating system written in the new VAX-11 instruction set. As a result, previously developed operating systems were not compatible, and an entirely new operating system had to be developed. Further limitations of the VAX-11 include a lack of non-privileged transitions between VAX-11 and PDP-11 instruction set modes, PDP-11 floating-point instructions, privileged execution in the PDP-11 instruction set mode, and input/output accessing in the PDP-11 instruction set mode.
Another prior art architecture which faces this limitation is the Intel® 386 processor (manufactured by Intel Corporation of Santa Clara, Calif.). The 386 processor expanded the Intel 286 processor (manufactured by Intel Corporation of Santa Clara, Calif.) architecture from 16 bits to 32 bits. However, the 386 processor did not include a new instruction set, but expanded the instruction set used by the 286 processor. In addition, the 386 processor provided only one method of implementing operating system type functions.
Another prior art architecture which faces this limitation is implemented in the MIPS R4000 processor manufactured by MIPS Computer Systems, Inc. of Sunnyvale, Calif. The R4000 processor expanded the R3000 processor to 64 bits. However, the R4000 processor did not include a new instruction set, but just expanded the instruction set used by the R3000 processor. In addition, the R4000 processor provided only one method for providing operating system type functions.
SUMMARY OF THE INVENTION
A processor having two system configurations is provided. The apparatus generally includes an instruction set unit, a system unit, an internal bus, and a bus unit. The instruction set unit, the system unit, and the bus unit are coupled together by the internal bus. The system unit is capable of selectively operating in one of two system configurations. The first system configuration provides a first system architecture, while the second system configuration provides a second system architecture. The bus unit is used for sending and receiving signals from the instruction set unit and the system unit. According to another aspect of the invention, the instruction set unit is capable of selectively operating in one of two instruction set configurations. The first instruction set configuration provides for the execution of instruction belonging to a first instruction set, while the second instruction set configuration provides for the execution of instructions belonging to a second instruction set.
REFERENCES:
patent: 5481693 (1996-01-01), Blomgren et al.
patent: 5484684 (1996-01-01), Richter, et al.
patent: 5530881 (1996-06-01), Inagami et al.
patent: 5542059 (1996-07-01), Blomgren
patent: 5574927 (1996-11-01), Scantlin
patent: 5598546 (1997-01-01), Blomgren
patent: 5740461 (1998-04-01), Jaggar
patent: 5765206 (1998-06-01), Hohensee et al.
patent: 5802382 (1998-09-01), Greenberger et al.
patent: 5815686 (1998-09-01), Earl et al.
patent: 5854913 (1998-12-01), Goetz et al.
patent: 5953520 (1999-09-01), Mallick
patent: 5968162 (1999-10-01), Yard
patent: 6021265 (2000-02-01), Nevill
Shanley, Tom and Anderson, Don,ISA System Architecture, Chapters 5, 8, 10, 11, and 18, Published by Mindshare, Inc. Second Edition Oct. 1993.
i486 Microprocessor Programmer's Reference Manual, Intel Corporation, 1990, pp. 1-1-1-9, 2-2-2-24,3-1-3-45,4-1-4-11, 5-1-5-25, 6-1-6-25, 7-1-7-15, 8-1-8-8, 9-1-9-26, 19-1-19-6 21-1-21-5, 22-1-22-12, 23-1-23-15, 24-1-24-8, 26-1-26-289.
Kane, Gerry and Heinrich, Joe,MIPS RISC Architecture, pp. 1-1 -4-30, 6-1 -6-57, 9-1, 9-1 -9-12, Published by Prentiss-Hall, Inc. 1992.
Wyant, Gregg and Hammerstrom, Tucker,How Microprocessors Work, Intel Corporation 1994, pp. 78-102, 199-185.
Alpert Donald
Hammond Gary
Kahn Kevin
Sharangpani Harsh
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kim Kenneth S.
LandOfFree
Address translation with/bypassing intermediate segmentation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Address translation with/bypassing intermediate segmentation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address translation with/bypassing intermediate segmentation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2489319