Address translation unit supporting variable page sizes

Details Address translation unit supporting variable page sizes Address translation unit supporting variable page sizes

1998-05-07

2001-03-20

Yoo, Do (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S206000, C711S203000, C711S205000, C711S212000, C711S211000

Reexamination Certificate

active

06205530

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an address translation unit which supports a variety of page sizes.
2. Description of the Related Art
In managing partitioning of a segment into page sizes in a memory management unit (MMU), the address translation unit generates a 20-bit physical address in order to support a 4K page size because of using upper 20 bits of a 32-bit linear address for partitioning the page; a 12-bit physical address is generated in order to support a 1M page size because of using upper 12 bits of the 32-bit linear address for partitioning the page; a 11-bit physical address is generated in order to support a 2M page size because of using upper 11 bits of the 32-bit linear address for partitioning the page; and a 10-bit physical address is generated in order to support a 4M page size because of using upper 10 bits of the 32-bit linear address for partitioning the page.
FIG. 1
is a block diagram illustrating a conventional address translation unit supporting the variety of page sizes in the MMU. As shown in
FIG. 1
, the conventional micro-processor has a plurality of translation look aside buffer (TLB)
12
,
13
,
14
and
15
for supporting the page sizes of 4K, 1M, 2M, and 4M bytes respectively.
And, a page unit controller
11
provides the corresponding TLB with the corresponding linear address of the 32-bit linear address in response to the page sizes, and applies a 2-bit page size select signal to a physical address selector
16
.
The physical address selector
16
selects one of the respective physical addresses outputted from each TLB in response to the page size select signal applied from the page unit controller
11
and outputs the selected physical address.
As described above, in the conventional address translation unit, routing and gate loads are bigger because the 32-bit linear address which was generated at the MMU is inputted to every TLB, and the conventional address translation unit needs the physical address selector in order to select one of the respective physical addresses which are outputted from each TLB. Therefore, the conventional address translation unit is difficult to the address translation of high speed and needs much area in order to realize TLBs.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an address translation unit which carries out the address translation with variable page sizes at high speed, and which can be realized to minimum area.


REFERENCES:
patent: 5263140 (1993-11-01), Riordan
patent: 5479627 (1995-12-01), Khalidi et al.
patent: 5526504 (1996-06-01), Hsu et al.
patent: 5530824 (1996-06-01), Peng et al.
patent: 5604879 (1997-02-01), Beavers et al.
patent: 5617554 (1997-04-01), Alpert et al.
patent: 5752275 (1998-05-01), Hammond
patent: 5784707 (1998-07-01), Khalidi et al.
patent: 5796978 (1998-08-01), Yoshioka et al.
patent: 5802341 (1998-09-01), Kline et al.
patent: 5835963 (1998-11-01), Yoshioka et al.
patent: 5907867 (1999-05-01), Shinbo et al.
patent: 5946716 (1999-08-01), Karp et al.
patent: 5956756 (1999-09-01), Khalidi et al.
patent: 5963984 (1999-10-01), Garibay, Jr. et al.

Affiliated with

Also associated with

Rating

Address translation unit supporting variable page sizes does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address translation unit supporting variable page sizes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address translation unit supporting variable page sizes will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2445257