Address translation unit employing a victim TLB

Details Address translation unit employing a victim TLB Address translation unit employing a victim TLB

1994-11-08

1998-05-12

Robertson, David L.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711122, G06F 1200

Patent

active

057522740

ABSTRACT:
An address translation unit is disclosed employing a direct-mapped translation lookaside buffer and a relatively small, associative victim translation lookaside buffer for translating linear addresses to physical addresses expediently and avoiding thrashing, without requiring large amounts of hardware and space.

REFERENCES:
patent: 5261066 (1993-11-01), Jouppi et al.
patent: 5555395 (1996-09-01), Parks
patent: 5574877 (1996-11-01), Dixit et al.
Cyrix 6x86.TM. Processor Data Book, Cyrix Corporation, pp. 1-14 to 1-15 and 2-45 to 2-52, 1996.
Norman P. Jouppi : Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. The 17th Annual International Symposium on Computer Architecture.

Affiliated with

Also associated with

Rating

Address translation unit employing a victim TLB does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address translation unit employing a victim TLB, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address translation unit employing a victim TLB will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-996863