Address translation system having first and second translation l

Details Address translation system having first and second translation l Address translation system having first and second translation l

1997-12-24

2000-10-24

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711 3, 711128, 711129, 711144, 711145, 711137, 711169, G06F 1210

Patent

active

061382256

ABSTRACT:
A memory system for providing rapid access to cached data includes a cache, a first TLB that stores address translation entries in a truncated form for fast access to data in the cache, and a second TLB that stores full address translation entries for accurate translation. The first TLB generates the tentative physical address quickly and initiates access to the cache using the tentative physical address. A way identified using the tentative physical address is read out of the cache and compared with a validated physical address provided by the second TLB. The initiated access is allowed to complete when the tentative and validated physical addresses match.

REFERENCES:
patent: 5179674 (1993-01-01), Williams et al.
patent: 5412787 (1995-05-01), Forsyth et al.
patent: 5900022 (1999-05-01), Kranich
patent: 5938761 (1999-08-01), Patel et al.
patent: 5956752 (1999-09-01), Mathews
patent: 6065091 (2000-05-01), Green

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