Address-translation method and system for translating effective

Details Address-translation method and system for translating effective Address-translation method and system for translating effective

1997-09-10

1999-08-17

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711206, G06F 1210

Patent

active

059408731

ABSTRACT:
An address-translation method is provided for efficiently translating effective addresses into physical addresses in X-86 based computers. In this method and system, when an effective address is generated, a segment base is then generated from a segment-descriptor cache memory in response to a selector address from the microcode. The segment base is added to the effective address to thereby obtain a linear address and a carry from the addition of the low-order portions of the segment base and the effective address. This carry is added to the high-order portion of the effective address to thereby obtain a comparison effective address. The comparison effective address and the segment base are then compared with a set of predetermined address values in a Translation Lookaside Buffer. If there is a match, a corresponding page base will be generated. The page base is then combined with the low-order portion of the linear address to thereby obtain the desired physical address. This address-translation method and system can speed up the access to the main memory since the address-translation and the linear address computation are proceeded in parallel, and also allow an increase in the hit ratio since the comparison process carried out in the Translation Lookaside Buffer involves the segment base from the segment-descriptor cache memory.

REFERENCES:
patent: 4631660 (1986-12-01), Woffinden et al.
patent: 5630088 (1997-05-01), Gupta et al.
patent: 5652872 (1997-07-01), Richter et al.

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