Address translation method and mechanism using physical address

Details Address translation method and mechanism using physical address Address translation method and mechanism using physical address

1995-06-02

1999-04-20

Downs, Robert W.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711200, 711201, 711203, 711206, 711204, 711208, G06F 1210, G06F 1206

Patent

active

058955038

ABSTRACT:
An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

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The Multics System, Elliott Organick, 1972, pp. 6-7, 38-51.
DPS-8 Assembly Instructions, Honeywell Corporation, Apr., 1980, Chapters 3 and 5.

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