Address translation logic for use in a GPS receiver

Details Address translation logic for use in a GPS receiver Address translation logic for use in a GPS receiver

2006-06-20

2006-06-20

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C342S357490, C342S357490, C342S357490, C375S150000

Reexamination Certificate

active

07065629

ABSTRACT:
The address translation logic of the present invention is incorporated in a global positioning system (GPS) receiver and operates to group data in memory based on translating the address from a direct memory access controller. The data includes post-correlated samples of the correlation of a signal with a generated frequency and a generated code having a plurality of time offsets. In general, the address translation logic organizes the data such that each element of the data associated with particular ones of the plurality of time offsets are grouped together in order to improve the efficiency of performing a fast Fourier transform of the data. In addition, the address translation logic allows the transfer of data from correlation circuitry to memory, from the memory to an FFT module, and from the FFT module to the memory using standard DMA controllers.

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Starzyk, J.A. and Zhu, Z., “Averaging Correlation for C/A Code Acquisition and Tracking in Frequency Domain,” Proceedings of the 44thIEEE 2001 Midwest Symposium on Circuits and Systems, vol. 2, pp. 905-908, Dayton, Ohio, Aug. 14-17, 2001.

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