Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1996-05-21
1999-08-17
Cabeca, John W.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711203, 711173, 709216, 71280028, G06F 906
Patent
active
059408707
ABSTRACT:
An address translation method for use in a system including a plurality of cluster nodes and including the steps of: at a source node, receiving over a first network a communication with a first destination address having an index portion and an offset portion, wherein the index portion includes a partition number portion; providing an address mapping table which maps a plurality of indexes to a corresponding plurality of node ID's, each of the plurality of node ID's identifying a different one of the plurality of cluster nodes; using the index portion from the first destination address as an index into the address mapping table to identify a node ID, wherein the identified node ID identifies a destination node; appending the identified node ID to the first destination address to generate a second destination address; and using the second destination address to send information to a second network of the destination node.
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Chan Cheng-Sheng
Chi Hsin-Chou
Maa Yeong-Chang
Cabeca John W.
Encarnacion Yamir
Industrial Technology Research Institute
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