Electrical computers and digital processing systems: memory – Address formation – Operand address generation
Reexamination Certificate
2001-06-01
2003-11-11
Robertson, David L. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Operand address generation
C711S220000, C711S153000
Reexamination Certificate
active
06647483
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for address translation circuits generally and, more particularly, to an address translation circuit for multiple processors utilizing a single code image stored in a shared memory region.
BACKGROUND OF THE INVENTION
Complex embedded control systems often incorporate multiple processors. Each processor has a local block of private memory where a limited amount of code and data unique to that processor are stored. All of the processors also have access to an external block of shared memory where more code and more data are stored. The shared memory provides greater storage capacity than the private memory.
Each processor executes a common binary code image to manipulate the data allocated to the processor. To avoid conflicts between processors within the shared memory, each processor is mapped to a unique address range within the shared memory. Consequently, each processor executing code from the shared memory must have a dedicated copy of the code stored in the shared memory. The dedicated copy of the code must reside within the unique address range for the respective processor. A result is that multiple copies of the same code image must be stored for the multiple processors thus consuming the shared memory. The multiple code images and address mapping, in turn, adds complexity to software management/configuration process for the system.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a processor and a translation circuit. The processor may be configured to present a first address. The translation circuit may be configured to (i) determine a mask and an offset, (ii) mask the first address to produce a first masked address, (iii) mask a second address to produce a second masked address, (iv) compare the first masked address with the second masked address, and (v) add the offset to the first address to present a third address in response to the first masked address being at least as great as the second masked address.
The objects, features and advantages of the present invention include providing a method and/or architecture for address translation circuits that may (i) allow multiple processors to utilize a single code image while providing unique shared memory data storage, (ii) require less memory to store code images, and/or (iii) simplify software configuration management.
REFERENCES:
patent: 6212604 (2001-04-01), Tremblay
patent: 6505269 (2003-01-01), Potter
Webster's Ninth New Collegiate Dictionary; © 1985; entry for —may—; pp. 734-734.*
Microsoft Press Computer Dictionary, 2nd ed.; © 1993; entry for —byte—, p. 59.*
IEEE 100: The Authoritative Dictionary of IEEE Standard Terms, 7th ed.; ©2000, entry for —byte—; p. 132.
Clegg Roger T.
Hoglund Timothy E.
Ortega William M.
LSI Logic Corporation
Maiorana PC Christopher P.
Robertson David L.
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