Address translation buffer system and method for invalidating ad

Electrical computers and digital processing systems: memory – Address formation – Address mapping

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711 6, G06F 1210

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active

059241276

ABSTRACT:
An address translation buffer system in which a searching time of an address translation buffer is shortened. The address translation buffer includes an address translation buffer connected to a translation table for translating a virtual address to a real address, the address translation buffer containing a plurality of columns holding a plurality of entries each having a pair of the virtual address and the real address translated based on the translation table and also having a virtual machine classification indicative of a type of the virtual address, a plurality of column control circuits for specifying columns of the address translation buffer with a combination of a lower part of the virtual address and the virtual machine classification as an entry, and circuits, in accordance with an invalidation instruction for purging one of the entries of the address translation buffer, for searching one of the columns of the address translation buffer having one of the entries of the address translation buffer coincided with the virtual machine classification entry of the invalidation instruction and for invalidating the entry including a specified field. It is unnecessary to search a group of columns having values other than the specified virtual machine classification.

REFERENCES:
patent: 4456954 (1984-06-01), Bullions, III et al.
patent: 4779188 (1988-10-01), Gum et al.
patent: 4816991 (1989-03-01), Watanable et al.
patent: 5317705 (1994-05-01), Gannon et al.
patent: 5317710 (1994-05-01), Ara et al.
Coscarella et al., "System for Purging TLB" IBM Technical Disclosure Bulletin, vol. 24, No. 2, Jul. 1981, pp. 910-911.

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