Address translation

Details Address translation Address translation

2003-06-02

2004-12-14

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S052000

Reexamination Certificate

active

06832274

ABSTRACT:

FIELD
The present invention is directed to arrangements for queuing/tracking of transaction portions to reduce latency.
BACKGROUND
Often times within computing systems, and especially within bridging devices, transactions such as read or write requests are passed between differing devices (e.g., interfaces) using queue arrangements. One arrangement is to let each device (e.g., interface) handle/process each respective transaction independently from all other devices, and to pass a transaction to a next sequential device once the device's handling/processing of the transaction is complete. However, during research leading to the present application, it was found that such independent/sequential passage and handling/processing of transactions by sequential devices are disadvantageous in that a latency to move a transaction through the system is not minimized. Accordingly, what is needed is a new and improved approach for the handling of transactions passed from device-to-device within a system.


REFERENCES:
patent: 5781431 (1998-07-01), Duret et al.
patent: 6453357 (2002-09-01), Crow et al.
patent: 6539439 (2003-03-01), Nguyen et al.
patent: 6601117 (2003-07-01), Dahlen et al.
patent: 6625707 (2003-09-01), Bormann

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