Address transition detector for fast flash memory device

Details Address transition detector for fast flash memory device Address transition detector for fast flash memory device

2007-09-11

2007-09-11

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S082000, C326S086000

Reexamination Certificate

active

11303863

ABSTRACT:
An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbiasand Nbiasnodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the Pbiasnode and the Nbiasnode. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.

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