Address transition circuit for a memory

Details Address transition circuit for a memory Address transition circuit for a memory

1998-01-22

1999-04-27

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Bridge

36518905, G11C 700

Patent

active

058986413

ABSTRACT:
A resettable latch circuit provides a modified address transition detection (XATD) signal in response to receiving an address-change input pulse signal at a SET input terminal thereof. A RESET input terminal for the latch circuit receives a delayed reset signal from a resettable delay circuit which has its input terminal coupled to the output terminal of the resettable latch circuit to receive the XATD signal. The resettable delay circuit includes a reset control signal terminal to which is coupled an inverted address-change input pulse. One embodiment of the resettable delay circuit includes a series of inverters and MOSFET load resistors as well as shunt MOSFET transistors turned on by the address-change signal to shunt the output terminals of the inverters and reset the delay line. The SET input terminal of the latch circuit also receives a chip-select-change signal pulse which is similar to the address-change pulse.

REFERENCES:
patent: 5706246 (1998-01-01), Choi et al.
patent: 5708625 (1998-01-01), Sato et al.

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