Address test pattern generator for burst transfer operation of a

Details Address test pattern generator for burst transfer operation of a Address test pattern generator for burst transfer operation of a

1995-08-22

1998-11-10

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

711200, 711202, 711105, G06F 926, G06F 1210

Patent

active

058359699

ABSTRACT:
An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a semiconductor device under test during a test process in real time and generates column addresses for the device under test by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, Z address signal, and an operation mode control signal is arranged, a conversion memory that outputs certain conversion table contents is arranged, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with the burst length control signal. In another aspect, the address pattern generator includes a counter that loads the lower address signal from the Y address generator section for the sequential mode and loads a fixed value for the interleave mode, an exclusive OR gate that provides an output signal of the counter to an input terminal and the lower address signal from the Y address generation section to the other input terminal, and a multiplexer that selects the output signal of the counter for the sequential mode and the output signal of the exclusive OR gate for the interleave mode.

REFERENCES:
patent: 4958345 (1990-09-01), Fujisaki
patent: 4958346 (1990-09-01), Fujisaki
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5410687 (1995-04-01), Fujisaki et al.
patent: 5412793 (1995-05-01), Kreifels et al.
patent: 5450364 (1995-09-01), Stephens, Jr. et al.
patent: 5481671 (1996-01-01), Fujisaki
patent: 5511029 (1996-04-01), Sawada et al.

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