Address space architecture for multiple bus computer systems

Details Address space architecture for multiple bus computer systems Address space architecture for multiple bus computer systems

1996-06-24

1998-11-10

Harvey, Jack B.

395309, 395308, G06F 1300

Patent

active

058357386

ABSTRACT:
An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.

REFERENCES:
patent: 4325118 (1982-04-01), DeVita et al.
patent: 4802085 (1989-01-01), Levy et al.
patent: 4845611 (1989-07-01), Turlakov et al.
patent: 5113369 (1992-05-01), Kinoshita
patent: 5287531 (1994-02-01), Rogers, Jr. et al.
patent: 5367689 (1994-11-01), Mayer et al.
patent: 5379384 (1995-01-01), Solomon
patent: 5396602 (1995-03-01), Amini et al.
patent: 5418930 (1995-05-01), Swarts
patent: 5423009 (1995-06-01), Zhu
patent: 5440698 (1995-08-01), Sindhu et al.
patent: 5471632 (1995-11-01), Gavin
patent: 5509126 (1996-04-01), Oprescu et al.
patent: 5590378 (1996-12-01), Thayer et al.

Affiliated with

Also associated with

Rating

Address space architecture for multiple bus computer systems does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address space architecture for multiple bus computer systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address space architecture for multiple bus computer systems will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1526897