Address sensitive memory testing

Details Address sensitive memory testing Address sensitive memory testing

1993-03-10

1994-10-18

Nguyen, Hoa T.

Excavating

371 401, 371 491, G11C 2900

Patent

active

053575210

ABSTRACT:
A method for testing directly addressable memory in a computer system uses address sensitive test data. When a memory error occurs, or when an initial testing of the memory indicates an error, the affected locations are retested with selected address sensitive memory test patterns. Proper address sensitive pattern selection allows all of the data bits, ECC data bits and address parity bits to be tested.

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Method for Address Fault Detection, IBM Technical Disclosure Bulletin, vol. 32, No. 1, Jun. 1989.

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