Address selective emulation routine pointer address mapping syst

Details Address selective emulation routine pointer address mapping syst Address selective emulation routine pointer address mapping syst

1994-09-26

1997-09-16

Harvey, Jack B.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711 3, 711206, G06F 1210

Patent

active

056689691

ABSTRACT:
An address selective address mapping system comprises an address translation circuit, a central processing unit (CPU), a data cache, and a memory. The address outputs of the CPU are coupled to a first address bus, while the address inputs of the data cache and memory are coupled to a second address bus. The address translation circuit's inputs are coupled to the first address bus, and the address translation circuit's outputs are coupled to the second address bus. The CPU sends a pointer address via the first address bus to the address translation circuit. The address translation circuit determines whether the pointer address indicates that the next source instruction is within the subset of the most frequently executed source instructions. If so, the address translation circuit maps the pointer address to an address within the data cache. If not, the pointer address is routed through the address translation circuit unchanged. The pointer address is next routed to the data cache and to the RAM via the second address bus. If the pointer address was mapped to a data cache address, the data cache outputs the pointer to the next emulation routine on the data bus. If the pointer address was not mapped to a data cache address, the pointer to the next emulation routine is output to the data bus at the data outputs of the memory. The present invention also includes a method for manufacturing an address selective address mapping system.

REFERENCES:
patent: 3698007 (1972-10-01), Malcolm et al.
patent: 5255384 (1993-10-01), Sachs et al.
patent: 5392408 (1995-02-01), Fitch
McBride, M., "Microprogrammable Chip Set Emulates Mainfraime Processing", Electronic Design, Aug. 1984, pp. 229-234, 236, 238, 240.
"High Performance Dual Architecture Processor", IBM Technical Disclosure Bulletin, Feb. 1993, pp. 231-234.

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