Address selection for testing of a microprocessor

Details Address selection for testing of a microprocessor Address selection for testing of a microprocessor

2006-05-16

2006-05-16

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C713S001000, C713S002000, C714S030000

Reexamination Certificate

active

07047444

ABSTRACT:
A microprocessor with built-in test, comprising: a register for retaining a test address of a test program; a next address generation logic for generating a command address of a command scheduled to be executed next, based on a command address of a command to be executed next; a first multiplexer for selecting, based on a test mode signal, any one of a boot address specifying a bootstrap program and the test address; a second multiplexer for selecting, based on a reset signal, any one of the command address of the command scheduled to be executed next and the address selected by the first multiplexer; and a program counter for retaining the address selected by the second multiplexer and for outputting the retained address to the next address generation logic as the command address of the command to be executed next.

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