Address selection circuit and semiconductor memory device...

Details Address selection circuit and semiconductor memory device... Address selection circuit and semiconductor memory device...

2003-04-24

2004-08-24

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S194000, C365S230080

Reexamination Certificate

active

06781919

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device such as a synchronous dynamic random-access memory (SDRAM). More particularly, the invention relates to an address selection circuit capable of quickly generating an address selection signal, and to a semiconductor memory device capable of high-speed access, including the first access in a burst access.
2. Description of the Related Art
FIG. 10
shows the structure of a conventional SDRAM, mainly showing the structure of the circuits that generate a column address selection signal from an externally input address signal, and omitting the circuits that generate a row address selection signal and perform data input and output.
The conventional SDRAM in
FIG. 10
has six input transistor-transistor-logic buffers (TTL BUF)
10
, five latch circuits
11
, a mode register (REG)
12
, a clock driver
13
, a pair of delay circuits
14
,
15
for timing control, a command decoder (DEC)
16
, a column address counter control clock generator (CLK GEN)
17
, a column address (COL ADDR) counter
18
, a carry generator (CARRY GEN)
19
, a burst length counter
110
, a column address pre-decoder (COL ADDR PRE-DEC)
111
, a column address decoder (COL ADR DEC)
112
, and a memory cell array
113
.
The input TTL buffers
10
input a clock signal CLK, a chip select command signal /CS, a row address strobe command signal /RAS, a column address strobe command signal /CAS, a write enable command signal /WE, and an address signal ADD, the slashes indicating signals that are active low. The command signals and the address signal are passed to the latch circuit
11
. To indicate that they have been buffered, the signals input to the latch circuits
11
are denoted CSb, RASb, CASb, WEb, and ADD_BUF. The buffered address signal ADD_BUF may be a parallel multiple-bit signal.
FIG. 11A
shows the structure of the latch circuits
11
, while
FIG. 11B
indicates the meaning of transistor symbols. For the CASb latch circuit
11
, for example, the input signal DIN in
FIG. 11A
is the CASb signal output from the /CAS input TTL buffer
10
in
FIG. 10
, the output signal denoted DOUT in
FIG. 11A
is the signal denoted CASINb in
FIG. 10
, and the output signal denoted DOUTb in
FIG. 11A
is the signal denoted CASIN in FIG.
10
.
The latch circuit
11
in
FIG. 11A
comprises inverters
113
,
114
,
118
,
119
,
122
,
123
,
124
,
125
, n-channel transistors
116
,
120
, and p-channel transistors
117
,
121
. Transistors
116
and
117
form a transmission gate TG
12
; transistors
120
and
121
form a transmission gate TG
13
. Inverters
118
and
119
form a master latch circuit; inverters
122
and
123
form a slave latch-circuit.
FIG. 12
shows the structure of a one-bit section of the column address counter
18
, comprising inverters
126
,
127
,
130
,
131
,
134
,
135
,
139
,
140
,
143
,
144
,
145
,
146
, n-channel transistors
128
,
132
,
138
,
142
, p-channel transistors
129
,
133
,
137
,
141
, and an exclusive-OR gate
136
. Inverters
130
and
131
form a master latch circuit MFF
1
for an externally input address bit; inverters
139
and
140
form a master latch circuit MFF for an internally generated address bit; inverters
143
and
144
form a slave latch circuit. Transistors
128
and
129
form a transmission gate TG
14
; transistors
132
and
133
form a transmission gate TG
15
. Transistors
137
and
138
form a transmission gate TG
16
; transistors
141
and
142
form a transmission gate TG
17
.
Operation of the Conventional SDRAM
FIG. 13
is a timing diagram of the main signals illustrating the operation of the conventional SDRAM in
FIG. 10
up to the generation of a column address selection signal.
FIG. 13
shows an example of the signal waveforms when the burst length is four and the burst type is sequential. The operation of the conventional SDRAM up to the generation of the column address selection signal will be described below with reference to
FIGS. 10-13
.
The externally input clock signal CLK passes through the CLK input TTL buffer
10
and is input as a clock signal CLK_BUF to the clock driver
13
. The clock driver
13
generates two clock signals with complementary logic at substantially the same time: a signal CLK_BUFD having the same logic as the input clock signal CLK, and a signal CLK_FFb having inverted logic, as shown in FIG.
13
. Clock signal CLK_BUFD is input to timing control delay circuit
14
, and clock signal CLK_FFb is input to the latch circuits
11
.
The clock signal CLK_BUFD input to delay circuit
14
is delayed and becomes a control clock signal CLK_BUFD
1
(FIG.
13
). This control clock signal CLK_BUFD
1
is input to the column address counter control clock generator
17
and the burst length counter
110
.
The externally input command signal /CAS passes through the /CAS input TTL buffer
10
and is input as a command signal CASb to the CASb latch circuit
11
.
The logic transitions of the externally input command signal /CAS occur at intervals longer than a setup time tSI and hold time tHI from rising edges of the externally input clock signal CLK (FIG.
13
). More specifically, the command signal /CAS goes to the Low level earlier than a rising edge of the clock signal CLK by at least the setup time tSI and returns to the High level later than the rising edge of the clock signal CLK by at least the hold time tHI (FIG.
13
). The other command signals /CS, /RAS and /WE are also input in this way.
In the CASb latch circuit
11
(FIG.
11
A), when clock signal CLK_FFb is High, transmission gate TG
12
is switched on and transmission gate TG
13
is switched off. In this state, the input command signal CASb (DIN in
FIG. 11A
) is latched in the master latch circuit formed by inverters
118
and
119
. When the externally input clock signal CLK goes to the High level, clock signal CLK_FFb goes to the Low level. In synchronization with the falling edge of clock signal CLK_FFb, transmission gate TG
12
switches off and transmission gate TG
13
switches on, so the command signal CASb is latched in the slave latch circuit formed by inverters
122
and
123
and becomes the output command signal CASIN (DOUTb in
FIG. 11A
) and its inverted logic signal CASINb (DOUT in FIG.
11
A), which are input to the command decoder
16
.
The command signals CASIN and CASINb are held and output continuously from the CASB latch circuit
11
until the next falling edge of clock signal CLK_FFb.
The command signals CASIN and CASINb are thus output continuously from the CASb latch circuit
11
, starting slightly after the first rising edge of the externally input clock signal CLK after input of the external command signal /CAS begins, and continuing until slightly after the next rising edge of the externally input clock signal CLK. For example, CASIN goes to the High level following a rising edge of the externally input clock signal CLK, and goes to the Low level following the next rising edge of the externally input clock signal CLK, as shown in FIG.
13
. The CSb, RASb, and WEb latch circuits
11
also operate in this way when command signals CSb, RASb, and WEb are input.
The command decoder
16
decodes the signals CSIN and CSINb received from the CSb latch circuit
11
, the signals RASIN and RASINb received from the RASb latch circuit
11
, the signals CASIN and CASINb received from the CASb latch circuit
11
, and the signals WEIN and WEINb received from the WEb latch circuit
11
, and outputs control signals RAS_CL, WE_CL, PRE_CL, MOD_CL, and CAS_CL. The SDRAM thereby enters an operating mode responsive to the command given by the input command signals /CS, /RAS, /CAS, and /WE.
Control signal MOD_CL goes High when a mode register command is input. Control signal RAS_CL goes High when a row active command is input. Control signal CAS_CL goes High when a read command is input. Control signals CAS_CL and WE_CL both go High when a write command is input. Control signal PRE_CL goes High when a precharge command is input. In

Affiliated with

Also associated with

Rating

Address selection circuit and semiconductor memory device... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address selection circuit and semiconductor memory device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address selection circuit and semiconductor memory device... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3308501