Address scrambling to simplify memory controller's address...

Details Address scrambling to simplify memory controller's address... Address scrambling to simplify memory controller's address...

2005-12-16

2009-02-17

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

C365S230020, C711S001000

Reexamination Certificate

active

07493467

ABSTRACT:
A memory controller receives a logical address of a data unit in a memory and scrambles the logical address according to an address scrambling scheme. The address scrambling scheme maps the logical address to time-multiplexed output of physical address pins of the memory controller. At least one of the physical address pins, which is to be mapped in a time phase in a baseline design, is to be unmapped in a corresponding time phase if a dimensional parameter of the memory changes. The logical address comprises row address bits and column address bits. All of the even row address bits may be mapped in a time phase for outputting the row address, and all of the odd row address bits may be mapped in another time phase for outputting the row address. Thus, configuration flexibility of the memory controller is improved.

REFERENCES:
patent: 5901105 (1999-05-01), Ong et al.
patent: 6199153 (2001-03-01), Razdan et al.
patent: 6260101 (2001-07-01), Hansen et al.
patent: 6850457 (2005-02-01), Cowles et al.
patent: 7133996 (2006-11-01), Ikeda et al.
Intel PXA27x Processor Family Developer's Manual, Section 6.4.2.3, “SDRAM Memory Size Options,” pp. 6-8 to 6-19.
Intel 82845 MCH for DDR Datasheet, Section 5.2.3, “Memory Address Translation and Decoding,” p. 111.

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