Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-04-05
2004-09-07
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C370S351000, C370S431000, C370S395720
Reexamination Certificate
active
06789176
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an address release method and to a common buffering device for an ATM (asynchronous transfer mode) switching system which employs the address release method.
2. Related Arts
An ATM switching system, which employs a common buffering device, manages for each output highway (HW) a write address and a read address which are used by the buffering device to implement a process for the switching of cells.
In
FIG. 10
is an example arrangement for a common buffering device included in an ATM switching system. A cell buffering module
1
is connected to a highway line side via highway interfaces
5
and
6
.
In the cell buffer module
1
, a centrally located cell buffer memory consists of 16 buffer memories MEM
0
to MEM
15
, and multiplexers (MUX)
100
to
115
and demultiplexers (DMUX)
200
to
215
, which are included in a number equivalent to the buffer memory count.
A write controller
2
and a read controller
3
are included as common buffer controllers, and an address buffer memory
4
is provided in association with the write controller
2
and the read controller
3
.
Each cell in the cell buffer memory has a capacity of 128K, and holds ATM cells stored in a bit slice form. Further, each bit of the 16 parallel bit sets constituting the ATM cell corresponds to one of the 16 buffer memories MEM
0
to MEM
15
which form the cell buffer memory.
Since in an ATM cell there are 64 bytes, if it is arranged into 16 parallel bit forms, its 32 clock width is the equivalent of the time for one cell. For bit slicing, a data set of 32 bits per clock, which is obtained by developing individual bits in parallel, is employed as the unit of control for processing.
That is, in
FIG. 10
, the ATM cell transmitted across each highway line for the highway interface
5
is divided into 16 bit slices each of which has a 32 bit width. The bit slices having the 32 bit widths are transmitted in parallel to the cell buffer module
1
.
In the cell buffer module
1
, identically numbered bits of the bit slices received in parallel are multiplexed by the multiplexers MUX. That is, in
FIG. 10
, for example, of the 16 bit slices the multiplexer (MUX)
100
multiplexes the 1st bit which corresponds to the first bit of an ATM cell, and the multiplexer (MUX)
115
multiplexes the 16th bit slice.
The bit slices multiplexed by the multiplexers (MUX)
100
to
115
are stored in parallel in the 16 buffer memories MEM
0
to MEM
15
for corresponding bits. The storage address is set by the write controller
2
of the common buffer controller.
The storage address set by the write controller
2
is stored in the address buffer memory
4
. The read controller
3
of the common buffer controller provides, as a read address, an address which corresponds to a write address, and 16 bit slices having a 32 bit width are read in parallel from the read address.
The 16 bit slices read in parallel are separated by the demultiplexers (DMUX)
200
to
215
, and are transmitted via the highway interface
6
to the destination lines.
FIG. 11
is a diagram for explaining the procedures performed by the write controller
2
for setting and releasing the storage addresses. In
FIG. 11
, the ATM cells from the multiplexers (MUX)
100
to
115
are input (step SO) and TAG information for the cells is analyzed by the write controller
2
, and an empty address &agr; is defined as a write address &agr; (step S
1
) and is written in the address buffer memory
4
.
Then, the cell data are written at the write address &agr;, which is set in the memories MEM
0
to MEM
14
in the cell buffer module
1
(step S
2
). The write controller
2
transmits as a read address the write address to the read control circuits RC
1
to RCn, of the read controller
3
, which correspond to the highway lines along which cell data to be read from the TAG information for the cell
100
is written to the address &agr; (step S
3
).
The read control circuits RC
1
to RCn of the read controller
3
sequentially write received read addresses in the FIFO memory. The read control circuits RC
1
to RCn then access read addresses a set by corresponding lines in the order in which they are written, and read the cell data therefrom (step S
4
).
The read control circuits RC
1
to RCn further notify the write controller
2
of the read address &agr; at which cell data has been read (step S
5
).
Upon receipt of the read address &agr;, the write controller
2
deletes and releases a corresponding write address &agr; from the address buffer memory
4
(step S
6
).
As is described above, the write address of the cell buffer module
1
is released when the ATM cell is read from the buffer memories MEM
0
to MEM
15
by the read controller
3
and is transmitted to the highway line. The released address is stored as a write address for the ATM cell which will arrive next.
When the reading is performed along a specific line, and when the ATM cell is read from the buffer memory MEM
0
to MEM
15
and is transmitted to the line, the write address of the buffer module
1
is released and is stored as a write address for the ATM cell which will arrive next. In the conventional system, a problem will arise when the received ATM cell is a multi-address call for transmitting the same cell to a plurality of lines.
Specifically, when the ATM cell is a multi-address communication call, releasing the address is not a simple operation, even when the ATM cell is read from a specific line. The address can not be released unless the reading is completed for all the lines for which the ATM cell should be copied. To resolve this problem, various methods have been proposed.
As previously described, as its depth the cell buffer module
1
in
FIG. 10
has a capacity of 128K. Accordingly, the address buffer memory
4
has a large capacity. Therefore, while taking into account how the common buffer device which uses an LSI (large scale integration) is formed, providing such a large memory in the LSI is not advantageous.
An effective method by which this can be effected is for the large memory to be constituted by using an external memory. However, when this is done, another problem arises as a result of the difference in the access speed of the external memory and the signal processing speed of the LSI.
SUMMARY OF THE INVENTION
It is, therefore, one objective of the present invention to provide an address release method whereby, with a simple arrangement for which a high-speed memory is employed, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call, and a common buffering device can be used for an ATM switching system which employs this address release method.
To achieve the above objective, according to one aspect of the present invention, a method for releasing an address in a common buffering device includes the steps of:
setting for an ATM cell which is to be transmitted to a specific line a write address for the common buffer memory;
writing the ATM cell at the write address;
reading the ATM cell from an address which corresponds to the write address;
transmitting the ATM cell to the specific line; and
releasing the write address in the common buffering device.
Furthermore, as the feature of the present invention, in a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the plurality of multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.
According to another aspect of the present invention, when the destination line for the transmission of the ATM cell in the read control table does not match the plurality of multi-address lines set in the write control table, to update the read control table, a li
Furukoshi Masanobu
Sonoda Kazumasa
Uriu Shiro
Wakabayashi Tetsuaki
Bataille Pierre-Michel
Katten Muchin Zavis & Rosenman
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