Address re-mapping for memory module using presence detect data

Details Address re-mapping for memory module using presence detect data Address re-mapping for memory module using presence detect data

2001-01-30

2002-09-03

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S005000, C711S101000, C711S103000, C711S115000, C711S171000, C711S172000

Reexamination Certificate

active

06446184

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to memory modules for computer systems. More particularly, the invention relates to address re-mapping techniques such as, for example, for system level negotiation of an addressing mode of a memory module by dynamic control of the presence detect data.
BACKGROUND OF THE INVENTION
Computer memory comes in two basic forms: Random Access Memory (hereinafter RAM) and Read-Only Memory (hereinafter ROM). RAM is generally used by a processor for reading and writing data. RAM memory is volatile typically, meaning that the data stored in the memory is lost when power is removed. ROM is generally used for storing data which will never change, such as the Basic Input/Output System (hereinafter BIOS). ROM memory is non-volatile typically, meaning that the data stored in the memory is not lost even if power is removed from the memory.
Generally, RAM makes up the bulk of the computer system's memory, excluding the computer system's hard-drive, if one exists. RAM typically comes in the form of dynamic RAM (hereinafter DRAM) which requires frequent recharging or refreshing to preserve its contents. Organizationally, RAM data is typically arranged in bytes of eight data bits. An optional ninth bit, a parity bit, acts as a check on the correctness of the values of the other eight bits.
As computer systems become more advanced, there is an ever increasing demand for DRAM memory capacity consequently, DRAM memory is available in module form, in which a plurality of memory chips are placed on a small circuit card, which card then plugs into a memory socket connected to the computer motherboard or memory carrier card.
Examples of commercial memory modules are SIMMs
(Single In-line Memory Modules) and DIMMs (Dual In-line Memory Modules)
In addition to an ever increasing demand for DRAM capacity, different computer systems may also require different memory operating modes. Present memories are designed with different modes and operational features, such as fast page mode (FPM), extended data out (EDO), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), parity and non-parity, error correcting (ECC) and non error correcting, to name a few. Memories also are produced with a variety of performance characteristics, such as access speeds, refresh times and so on. Further still, a wide variety of basic memory architectures are available with different device organizations, addressing requirements and logical banks. As a result, some memory modules may or may not have features that are compatible with a particular computer system.
In order to address some of the problems associated with the wide variety of memory chip performance, operational characteristics and compatibility with system requirements, memory modules are being provided with presence detect (PD) data. PD data is stored in a non-volatile memory, such as an electrically erasable programmable read-only memory (EEPROM) on the memory module. A typical PD data structure includes 256 eight bit bytes of information. Bytes 0 through 127 are generally locked by the manufacturer, while bytes 128 through 255 are available for system use. Bytes 0-35 are intended to provide an in-depth summary of the memory module architecture, allowable functions and important timing information. PD data can be read in parallel or series form, but serial PD (SPD) is already commonly in use. SPD data is serially accessed by the system memory controller during boot up across a standard serial bus, such as an I
2
C™ bus (hereinafter referred to as a I2C bus). The system controller then determines whether the memory module is compatible with the system requirements and, if it is, will complete a normal boot. If the module is not compatible, an error message may be issued, or other action taken.
Some memory devices have the memory cells organized into a number of logical banks which can be individually addressed by the system memory controller. Control of bank selection is accomplished through the use of one or more Bank Address (BA) inputs. If the memory device bank organization is not the same as the system level addressing scheme, the memory module may be incompatible with the system requirements. For example, the system may need a two bank memory chip, but the memory module may include a memory device that is a four bank device.
It is desired, therefore, to provide a memory module that is more flexible in terms of its compatibility with different computer systems, and particularly that permits the computer system dynamically to negotiate available memory module functions and modes, especially an address re-mapping function.
SUMMARY OF THE INVENTION
The present invention contemplates, in one embodiment, a memory module that includes a plurality of memory devices associated with the module; each of said memory devices being configured as M banks; and a logic circuit for configuring the memory module to operate in a programmable addressing mode; said logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with said address inputs and bank address input signals corresponding to N bank memory devices; said logic circuit re-mapping at least one of said address inputs or bank address inputs as an additional bank address signal to the memory device.
The invention also contemplates the methods embodied in the use of such a memory module and, in another embodiment, a method for using an M bank memory device in a computer system that has N bank addressing, comprising the steps of:
a) inputting address signals from a system controller to a logic circuit, said address signals including a number of address inputs and a number of bank address signals;
b) re-mapping at least one of said address inputs as an additional bank address signal; and
c) providing said address inputs, bank address signals and said additional bank address signals as inputs to the memory device.
These and other aspects and advantages of the present invention will be readily understood and appreciated by those skilled in the art from the following detailed description of a preferred embodiments with the best mode contemplated for practicing the invention in view of the accompanying drawings.


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