Address pipelining for data transfers

Details Address pipelining for data transfers Address pipelining for data transfers

1997-11-20

2000-06-27

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710107, 710112, 710113, 710240, 710241, 710 4, 710 21, 710 27, 712 31, 711150, 711151, 711156, 711168, 711169, G06F 1300

Patent

active

060818603

ABSTRACT:
A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer. The design is configured to advantageously function in mixed systems which may include address-pipelining and non-address-pipelining slave devices.

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