Address pattern generator for burst address access of an SDRAM

Details Address pattern generator for burst address access of an SDRAM Address pattern generator for burst address access of an SDRAM

1998-01-30

1999-08-17

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

711200, 711105, 711218, 714718, 714719, 714742, 714743, G01K 3128

Patent

active

059408758

ABSTRACT:
An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM (SDRAM) is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a SDRAM during a test process in real time and generates column addresses for the SDRAM by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, a Z address signal, and an operation mode control signal, a conversion memory that outputs data based on a conversion table, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with a burst length control signal. In another aspect, the address pattern generator includes a counter that loads the lower address signal from the Y address generator section for the sequential mode while a fixed value for the interleave mode, an exclusive OR gate that receives an output signal of the counter to an input terminal and the lower address signal from the Y address generation section to the other input terminal, and a multiplexer that selects the output signal of the counter for the sequential mode and the output signal of the exclusive OR gate for the interleave mode.

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