Address match scheme for DRAM redundancy scheme

Details Address match scheme for DRAM redundancy scheme Address match scheme for DRAM redundancy scheme

1991-04-30

1994-03-08

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700, G11C 1300

Patent

active

052935647

ABSTRACT:
An address match scheme is disclosed which allows the alternate selection of fuses blown based on either logic ones or logic zeros in an address.

REFERENCES:
patent: 4714839 (1987-12-01), Chung
patent: 4729117 (1988-03-01), Osaka
patent: 4754434 (1988-06-01), Wang et al.
patent: 4791319 (1988-12-01), Tagami et al.
patent: 4829480 (1989-05-01), Seo
patent: 4860256 (1989-08-01), Devin et al.
patent: 4860260 (1989-08-01), Saito et al.
patent: 5107464 (1992-04-01), Sahara et al.

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