Address limit check apparatus with conditional carry logic

Details Address limit check apparatus with conditional carry logic Address limit check apparatus with conditional carry logic

1996-04-09

1998-07-28

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Slip control, misaligning, boundary alignment

36478603, G06F 1200

Patent

active

057874921

ABSTRACT:
An effective address limit checker reduces the logic delay in the limit checking path. The address limit checker comprises an effective address (EA) adder and limit check logic. The EA adder includes a first carry save adder receiving a displacement, an index and a base address for calculating an effective address, and a second carry select adder receiving partial sum and carry outputs of said first adder for calculating an effective address carry out. The outputs of the EA adder are input to the limit checking logic together with an address limit value and an addressability mode field. The limit checking logic includes a third adder for calculating first partial limit information based on the first adder results and the limit value, and a fourth adder for calculating second partial limit information based on the first adder results and the limit value and conditioned carry out values of the third adder. The third and fourth adders are each composed of a carry save adder and a carry select adder. Conditional carry logic responsive to output values of the third adder controls the operation of the fourth adder based on the addressability mode field. Limit exceeded logic responsive to the carry out of the fourth adder and the second adder asserts a limit check condition.

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