Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
1999-12-08
2001-06-19
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S230080, C365S233100, C711S167000, C711S118000, C711S118000, C711S118000
Reexamination Certificate
active
06249463
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an address latch enable signal control circuit for electronic memories. More particularly, the invention relates to an address latch signal control circuit for both volatile and nonvolatile memories which not only ensures correct address reading but also ensures certainty of the intention to acquire an address which is external to the memory.
It is known that volatile and permanent electronic memories point to one of their internal locations by using interposed structures, such as for example latch circuits or counters.
In order to operate correctly, these structures require suitable control signals which determine and allow the loading of a new address from outside the memory.
The control signal, usually known as ALE (Address Latch Enable), generally has several characteristics which are very important for its effectiveness and validity when it is necessary to operate in extreme conditions, such as for example those entailed by a high address acquisition rate, which introduces acquisition problems.
A first one of these characteristics is the duration of the control pulse. When this duration is too short, bad address capture conditions occur: at high rates, the pulse (control signal) is very narrow and address capture is unsteady.
A second characteristic is the filtering of noise-related pulses (spikes) which can lead to false and unintended address loadings.
A third characteristic of the control signal is to recognize authentic and non-authentic ALE pulses for the memory. For example, when a standby condition occurs, every activation of the ALE line is to be understood as being aimed at address capture activities on the part of another device that belongs to the system, but this address is not pertinent to the electronic memory being considered.
In normal and ideal operating conditions of the system, the above conditions, despite being stringent, are not difficult to meet, since it is sufficient to design them suitably during the construction of the system.
However, it is necessary to ensure that the ALE control signal is not independent of the other fundamental control signals of the memory, such as for example CE and RD.
For memories with an interleaved architecture, this last characteristic becomes particularly important, since synchronization among the various control signals introduces significant “sensitivities” which must be eliminated.
A first negative sensitivity is caused by return from a standby condition of the memory (i.e., when CEn switches from 1 to 0) while the ALE pulse is already active. In this situation, since the switching of the chip enable signal (CEn) occurs with a delay with respect to the ALE pulse, this causes a sort of “slicing” of the address capture pulse, consequently making said address capture critical.
If the switching delay of the CEn signal is excessive, this can even cause absence of the internal pulse (total suppression of the external pulse).
Another significant drawback occurs in the transition from the active step to the standby step (i.e., when the signal CEn switches from 0 to 1) when the ALE pulse is present. In this case, if the ALE pulse occurs too early with respect to the switching of the CEn signal, the external ALE pulse is interpreted incorrectly and, by generating an internal pulse, an unintended address capture occurs.
SUMMARY OF THE INVENTION
The aim of the present invention is to provide an address latch enable signal control circuit for electronic memories which allows to distinguish between address latch pulses related to the memory and address latch pulses intended for other units, in order to appropriately promote address capture operations.
Within the scope of this aim, an object of the present invention is to provide an address latch enable signal control circuit for electronic memories in which the duration of the address latch pulse is as short as possible yet sufficient to ensure correct address capture.
Another object of the present invention is to provide an address latch enable signal control circuit for electronic memories which allows to synchronize the address latch enable signal with the fundamental memory control signals, such as the CE signal and the RD signal.
Another object of the present invention is to provide an address latch enable signal control circuit for electronic memories which improves the performance of the memory during return from standby with the address latch enable pulse already active and during transition from the active step to the standby step while the address latch enable pulse is present.
Another object of the present invention is to provide an address latch enable signal control circuit for electronic memories which allows to extend the address latch pulse for a memory in order to improve the capture capability thereof.
Another object of the present invention is to provide an address latch enable signal control circuit for electronic memories which allows to filter noise pulses which can cause unwanted address loadings.
Another object of the present invention is to provide an address latch enable signal control circuit for electronic memories which is highly reliable, relatively easy to manufacture and at competitive costs.
This aim, these objects and others which will become apparent hereinafter are achieved by an address latch enable signal control circuit for electronic memories, characterized in that it comprises:
means for sensing an external address latch enable signal;
switching means connected in output to said sensing means;
address storage means, connected in output to said switching means and to said address sensing means;
said switching means being suitable to determine the switching between a first circuit path and a second circuit path for connection between said address sensing means and said address storage means;
said first circuit path connecting said sensing means directly to said storage means across said switching means;
said second circuit path connecting said sensing means to said storage means with delay means interposed, said delay means being suitable to produce a time delay in the connection between said address sensing means and said address storage means, said sensing means being suitable to generate an internal address latch enable signal meant to be stored in said storage means.
REFERENCES:
patent: 5548560 (1996-08-01), Stephens, Jr. et al.
patent: 5896341 (1999-04-01), Takahashi
Galanthay Theodore E.
Jenkens & Gilchrist P.C.
Nelms David
STMicroelectronics S.r.l.
Yoha Connie C.
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