Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-04-01
2003-01-14
Pham, Chi (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C711S217000
Reexamination Certificate
active
06507629
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an address generator, interleave unit, deinterleave unit, and transmission unit, and more particularly, is preferably applied to a radio communications system such as a portable telephone system.
2. Description of the Related Art
A radio communication system of this type is so structured that an area of communication service is divided into cells of a desired size and a base station is installed as a fixed radio station within each of the cells, and a portable telephone set serving as a mobile radio station communicates by radio with the base station of the cell in which it is located, thus implementing a so-called cellular system.
One of various communication systems between a portable telephone set and a base station is the code division multiple access (CDMA) system. The CDMA system assigns on the transmission side inherent pseudo random noise sequence (PN) codes composed of pseudo random series codes to each communication line and multiplies the PN code by the primary modulated signal, thereby diffusing the PN code over a wider bandwidth than the original frequency bandwidth (hereinafter referred to as the spread spectrum), and transmits the secondary modulated waves which have undergone the spread spectrum processing.
Such cellular system mobile station of the CDMA system adds cyclic redundancy check (CRC) codes to audio data at the time of transmission, performs convolutional coding (processing up to here is called encoding), and then, supplies thus obtained series of transmit symbols to an interleave processing circuit (hereinafter, referred to as an interleaver). The interleaver stores the series of transmit symbols in an internal memory in a prescribed write order, and reads out the series of transmit symbols in a read order different from the write order to rearrange the order of symbols at random, that is, performs interleave processing. The series of transmit symbols interleaved is modulated in a prescribed method and is transmitted as an analog transmit signal.
In addition, in the mobile station, each symbol of a series of receive symbols generated by converting the receive signal received at the time of reception into a digital signal is stored in the internal memory in a write order having the same pattern as the transmission side, and is read out in a read order different from the write order, to restore the order of symbols (hereinafter, referred to as deinterleaver). After this, the mobile station performs the Viterbi decoding and then error detection through the CRC codes.
In this case where the series of transmit symbols which have undergone the convolutional coding by the mobile station at the time of transmission does not have errors at random (uniform) in the transmission path but tends to cause burst (local) errors. If such burst errors exceed the error correction capability of the corresponding section, some errors remain uncorrected. To prevent such troubles, errors in the transmission path are distributed so that the receiving side can efficiently perform error correction processing by applying interleave processing to the series of transmit symbols.
When the above interleave processing is performed, in the interleaver
1
shown in
FIG. 1
, transmit symbol series data D
16
which has been subjected to convolutional coding processing is supplied as input data to a first interleave memory
2
and a second interleave memory
3
, eight bits by eight bits in parallel.
A memory switching controller
4
outputs a write address WA
1
generated by a write address counter
5
to only the first interleave memory
2
via a first address selector
6
. Accordingly, the first interleave memory
2
writes the transmit symbol series data D
16
into a predetermined area in an eight-bit unit according to the write address WA
1
.
Although the write address WA
1
is also outputted to a second address selector
10
, the write address WA
1
is not outputted to the second interleave memory
3
from the second address selector
10
because the second address selector
10
outputs read addresses under the control of the memory switching controller
4
.
Next the memory switching controller
4
transmits a read address RA
0
generated by a read address counter
8
of a read address generator
7
to an address conversion ROM
9
. The address conversion ROM
9
converts the read address RA
0
to a new read address RA
1
specified to rearrange the write order to a random order according to the read address RA
0
, then outputs the address RA
1
to only the first interleave memory
2
via the first address selector
6
.
Here the read address RA
1
is also outputted to the second address selector
10
. The read address RA
1
is not outputted to the second interleave memory
3
from the second address selector
10
because the second address sector
10
outputs the write address WA
1
under the control of the memory switching controller
4
.
The first interleave memory
2
reads the just written transmit symbol series data D
16
in an eight-bit unit according to the read address RA
1
and outputs the transmit symbol series data D
16
as interleaved converted data D
2
via a data selector
11
. Since the read address RA
1
is converted to a read address different from that used for write processing by the address conversion ROM
9
, the interleaved converted data D
2
is outputted.
The memory switching controller
4
, while reading the interleaved converted data D
2
from the first interleave memory
2
, outputs the write address WA
1
from the second address selector
10
to the second interleave memory
3
to write the next transmit symbol series data D
16
in the predetermined area of the second interleave memory
3
in a eight-bit unit according to the write address WA
1
.
When the memory switching controller
4
finishes reading the converted data D
2
from the first interleave memory
2
, it switches the second address selector
10
to output the read address RA
1
, which is outputted from the read address generator
7
, to the second interleave memory
3
via the second address selector
10
. Accordingly, the second interleave memory
3
reads the just written transmit symbol series data D
16
in an eight-bit unit according to the read address RA
1
and outputs the: transmit symbol series data D
16
as interleaved converted data D
3
via the data selector
11
.
At this time, the memory switching controller
4
, while reading interleaved converted data D
3
from the second interleave memory
3
, outputs the write address WA
1
from the first address selector
6
to the first interleave memory
2
. In this way, the memory switching controller
4
is so structured that, while it is reading the interleaved converted data D
2
from the first interleave memory
2
, it writes the transmit symbol series data D
16
into the second interleave memory
3
, and further, while it is reading the interleaved converted data D
3
from the second interleave memory
3
, writes the transmit symbol series data D
16
into the first interleave memory
2
, thus efficiently interleaving the input transmit symbol series data D
16
.
In this way, the conventional interleaver
1
needs to be provided with the address conversion ROM
9
in the read address generator
7
for interleave processing. The mobile station as a whole requires a deinterleaver (not shown) provided with the address conversion ROM
9
similar to that of the interleaver
1
, in addition to the interleaver
1
. As a result, the mobile station has a problem the amount of data to be stored in the address conversion ROM
9
is large as the patterns of the write/read address patterns which are used for interleave/deinterleave processing increase with increase of data, resulting in larger circuit scale.
As shown in
FIG. 2
where the same numerals are applied to parts corresponding to
FIG. 1
, in the interleaver
120
, a read address RA
3
generated by a read address counter
23
in a read address generator
121
is outputted to a first address selector
6
Burd Kevin M
Maioli Jay H.
Pham Chi
Sony Corporation
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