Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing
Reexamination Certificate
2001-12-21
2004-05-11
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Addressing
C345S098000, C345S104000
Reexamination Certificate
active
06734868
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to digital video and, more particularly, to Liquid Crystal Display (LCD) control.
BACKGROUND TECHNOLOGY
Reflective Liquid Crystal Display (RLCD) panels are usually built with sectionized digital video inputs. For example, a previously known RCDL panel of 1280×1024 pixels is interfacing digital video in the form of four sections of 320×1024 pixels each. Moreover, each section has independent 8-bit video inputs for odd and even pixels. For that reason, it is necessary to reorder pixels of every video line. This is normally implemented by reordering electronics, or so-called remapper, usually comprising three major elements: interleaver, pixel shuffler and corner turner.
The interleaver creates 32-bit quad-pixel groups (also known as, and hereinafter termed, “quadlets”) of only odd or only even video pixels. Such an interleaving is done for each of three colors (red, green and blue) and each of three 32-bit outputs, providing 320 quadlets per video line. The shuffler receives, on each of three inputs, quadlets sequentially numbered 0, 1, 2, 3 . . . 319 and outputs them in the sequence 0, 1, 80, 81, 160, 161, 240, 241, 2, 3, 82, 83 . . . 238, 239, 318, 319. In RLCD projectors wherein the rear projection mode is implemented rather than the front projection mode, every video line is mirror-reflected and the shuffler outputs quadlets in the sequence: 319, 318, 239, 238, 159, 158, 79, 78 . . . 81, 80, 1, 0. The corner turner then reorders 8-bit video pixels within each group of eight adjacent quadlets.
The operation carried out by the pixel shuffler can be represented as a matrix transposition. Then a matrix of 40×4 should be transposed where two adjacent quadlets represent one element of such a matrix. A pixel shuffler operating in the conventional manner (i.e., by the so-called Ping Pong method) includes two banks of SRAM 320×96 each. During a video line period one of the banks is filled with quadlets in the specified sequence as the other bank is read with reading address order 0, 1, 80, 81, 160, 161, 240, 241, 2, 3, 82, 83 . . . 238, 239, 318, 319. Although the Ping Pong method of pixel shuffling is very reliable, it requires 60K bits of SRAM and is thus quite memory expensive.
The present invention is directed to overcoming one or more of the problems or disadvantages associated with the relevant technology.
SUMMARY OF THE INVENTION
As will be more readily understood and fully appreciated from the following detailed description of the preferred embodiment, the present invention is embodied in a pixel shuffler having only one bank of 320×96 SRAM and incorporating a device termed an address generator, allowing the memory to operate in a read-modify-write mode. This means that any address location of memory is read and immediately overwritten with the new data. In this case, every new video line will require a new address order. Thus, as implemented, the invention allows the pixel shuffling function to be carried out with half the memory capacity of conventional systems.
REFERENCES:
patent: 5268681 (1993-12-01), Lin et al.
patent: 6215507 (2001-04-01), Nally et al.
patent: 6384809 (2002-05-01), Smith
patent: 6522319 (2003-02-01), Yamazaki
Dean John E.
Gornstein Viktor L.
Koninklijke Philips Electronics , N.V.
Tung Kee M.
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