Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
Reexamination Certificate
1993-11-19
2001-01-09
Yoo, Do Hyun (Department: 2759)
Electrical computers and digital processing systems: memory
Address formation
Incrementing, decrementing, or shifting circuitry
C711S200000, C711S201000, C711S202000, C711S203000, C711S212000, C711S213000, C711S214000, C711S215000, C711S216000, C711S217000, C711S218000, C711S220000
Reexamination Certificate
active
06173385
ABSTRACT:
MICROFICHE APPENDIX
This disclosure includes a microfiche appendix having 1 fiche and a total of 35 frames.
1. Field of the Invention
This invention relates to address generators and more specifically to an address generator for a “solid state disk” which is a random access memory device which appears to a host computer system to be a disk drive.
2. Description of the Prior Art
The well known SCSI interface is ideal for high performance solid state disks. Unlike ESDI or SMD interfaces, the SCSI interface presents the peripheral with the number of the desired logical block to be accessed. Solid State Disks (SSDs), based on contiguous random access (semiconductor) memory chips, can access the proper information based on the specified logical block. An example of an SSD (which however is not block-length oriented) is disclosed in U.S. Pat. No. 5,070,474.
Referring to the system diagram in
FIG. 1
, the SCSI host computer
10
presents the SSD
12
with a command to read or write along with the desired logical block and the number of blocks to be written or read on SCSI bus
14
. The SSD controller
16
must interpret this command received from SCSI interface
18
and set the DRAM memory array
22
(DRAM chips) to the appropriate starting address via address generator
26
. This is analogous to the seek time in a rotating (physical) disk drive. The controller
16
then reads or writes the proper number of blocks to the memory array
22
on address bus
24
. (Block-length oriented SSDs are known in the art.) Address generator
26
operates in response to signal AGEN from controller
16
.
SSD
12
also conventionally includes DMA (direct memory address) controller
30
and error correction circuitry
32
connected by various busses as shown. Also included is a backup interface
34
and backup physical disk
38
.
A difficulty arises due to the variable length of the logical blocks. Consider a typical host computer system
10
based on a logical block length of 512 bytes per block. Block zero begins at an address of zero, block one begins 512 bytes later, block two at 1024 bytes and so on. Should a second system be based upon a block size of 256 bytes per block these addresses would change. In this case block zero would still begin at byte zero, but block one would occur at byte
256
, block two at byte
512
and so on.
The method for locating the desired starting address is:
Starting Address=Desired Logical Block×Logical Block Length
While the method is simple, the magnitude of the variables causes difficulty. The SCSI read/write extended commands specify the desired logical block as a 32 bit variable. The logical block length is as large as 16 bits in a typical computer system. Normally this multiplication is performed in software in a microprocessor or microcontroller
16
using multiply functions or various shifting techniques. Such operations on variables of this magnitude can require many machine cycles on small (reasonably priced) microcontrollers. This results in long seek times which are undesirable in a solid state disk. Microcontrollers allowing 32 bit operations are expensive, difficult to embed and otherwise unnecessary for a typical SCSI peripheral.
SUMMARY OF THE INVENTION
The present invention in one embodiment includes a dedicated logic circuit for determining the desired starting address of an SSD operation (read or write). The circuit is a multiplier circuit which, as data block numbers are received by the multiplier, multiplies the data block number by a block size value to quickly generate the address. The block size value is (in one embodiment) programmed once, at power up of the SSD, with the appropriate value for the desired block size. (Alternatively the block size value is dynamically alterable after power up). The access time is in the submicrosecond range for any typical block size.
In a typical SCSI application where a physical (not solid state) disk drive is used, the speed limit of the system is fairly low due to the relatively slow access time of a physical disk drive. The same is true for the relatively slow access time for tape drives and other types of rotating magnetic memory. Thus in these cases, there is no need for a higher speed address generator than that provided in the prior art software address generation calculation, and so use of a dedicated multiplier logic circuit in a physical disk drive address generator would not appear generally to be useful.
REFERENCES:
patent: 5070474 (1991-12-01), Tuma et al.
patent: 5088031 (1992-02-01), Takasaki et al.
patent: 5179662 (1993-01-01), Corrigan et al.
patent: 5218691 (1993-06-01), Tuma et al.
patent: 5343426 (1994-08-01), Cassidy et al.
Tuma George B.
Tuma Wade B.
Disk Emulation Systems, Inc.
Klivans Norman R.
Nguyen Than
Skjerven Morrill & MacPherson LLP
Yoo Do Hyun
LandOfFree
Address generator for solid state disk drive does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Address generator for solid state disk drive, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address generator for solid state disk drive will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2447697