Pulse or digital communications – Miscellaneous
Reexamination Certificate
2000-04-03
2003-07-08
Vo, Don N. (Department: 2631)
Pulse or digital communications
Miscellaneous
C714S702000
Reexamination Certificate
active
06590951
ABSTRACT:
PRIORITY
This application claims priority to an application entitled “Address Generator and Address Generating Method for Use in Turbo Interleaver/Deinterleaver” filed in the Korean Industrial Property Office on Apr. 2, 1999 and assigned Serial No. 99-12859, the contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a turbo interleaver/deinterleaver in a radio communications system, and in particular, to an address generator and an address generating method for use in turbo interleaving/deinterleaving.
2. Description of the Related Art
A turbo encoder (i.e., an encoder using turbo codes) can be used as an encoder for a radio communications system such as a satellite system, the ISDN (Integrated Services Digital Network), a digital cellular system, W-CDMA (Wideband-Code Division Multiple Access), and IMT-2000 (CDMA 2000). The turbo encoder includes an interleaver, which randomizes the input information to the turbo encoder. The interleaver is a significant factor in the performance of the turbo encoder because it improves the distance property of the codewords.
FIG. 1
is a block diagram of a turbo encoder having a turbo interleaver to which the present invention is applied. For details, see U.S. Pat. No. 5,446,747 issued on Aug. 29, 1995.
In
FIG. 1
, the turbo encoder is comprised of a first constituent encoder
10
for encoding input frame data d
k
to Y
1
k
, an interleaver
30
for interleaving the input frame data d
k
, and a second constituent encoder
20
for encoding the output of the interleaver
30
to Y
2
k
. For the input of d
k
, the turbo encoder outputs X
k
without encoding, Y
1
k
through encoding, and Y
2
k
through interleaving and encoding. The first and second constituent encoders
10
and
20
can be RSC (Recursive Systematic Convolutional) encoders as are well-known in the field. The constituent encoders may vary in structure depending on their code rate.
The interleaver
30
, having an interleaver size equal to the data frame length, permutes the sequence of input data bits, and outputs the permuted data bits to the second constituent encoder
20
, thus reducing the correlation between the data bits.
The interleaver
30
includes an address generator
32
, a counter
34
, and an interleaver memory
36
. The interleaver memory
36
stores the input frame data dk according to write addresses received from counter
34
, and outputs the data according to read addresses received from the address generator
32
. The address generator
32
generates a read address, which is used for reordering data bits, and feeds the read address to the interleaver memory
36
. The read address is generated according to the length of an input data frame and a symbol clock signal. The counter
34
receives the symbol clock pulses and outputs the count value of the symbol clock pulses as a write address to the interleaver memory
36
. The interleaver
30
outputs the data stored in the interleaver memory
36
to the second constituent encoder
20
.
Various interleavers can be used as the inner interleaver for the turbo encoder, such as a PN (Pseudo Noise) random interleaver, a random interleaver, a block interleaver, a non-linear interleaver, or an S-random interleaver. These interleavers, however, use algorithms designed in an academic environment for the purpose of performance improvement, not algorithms designed from a practical perspective. These interleavers are often not viable because of the complexity of implementing them in hardware.
In the IMT-2000 specification and the IS-95C specification, a linear congruential sequence (LCS) turbo encoder constituted as shown in
FIG. 1
has recently been settled as the turbo encoder. Specifically, it has been provided that turbo codes should be used for a supplemental channel, which is a data transmission channel in the air interface of IMT-2000 and IS-95C, and for a data channel in an UMTS (Universal Mobile Telecommunications System) developed by the ETSI (European Telecommunications Standards Institute).
FIG. 2
is a block diagram of the address generator
32
shown in FIG.
1
.
Referring to
FIG. 2
, the lower 5 bits, or the Least Significant Bits (LSBs), of the output from the input counter
110
are fed to a look-up table
130
for storing an initial seed (C-values) of each group and a bit reverser
140
. The 5 lower bits indicate one of the 2
5
groups of the interleaving block, which is determined according to the interleaver size. The bit reverser
140
reverses the lower 5 bits and applies the reversed bits to the highest position, or Most Significant Bits (MSBs), of an address selection generator
160
. The lookup table
130
feeds an n-bit C-value, based on the inputted lower 5 bits, to a multiplication & modulo operating device
150
.
Meanwhile, the upper n bits, or MSBs, output from the input counter
110
are fed to a first adder
120
. Here, the upper n bits indicate one of 2
n
addresses in each group and are used as a variable for permuting data bits of the group. The first adder
120
adds 1 to the received upper n bits and applies the sum to the multiplication & modulo operating device
150
. The multiplication & modulo operating device
150
subjects the input n bits and the initial n-bit seed C of each group to multiplication and modulo addition, and then feeds the result to the address selection generator
160
. Modulo addition refers to retaining the lower n bits of the sum resulting from multiplying the output of the adder
120
by the output of the look-up table
130
. The address selection generator
160
forms an address in which the output of the bit reverser
140
is the upper 5 bits, MSBs, and the output of the multiplication & modulo operating device
150
is the lower n bits, LSBs, for turbo interleaving. If the address formed is larger than or equal to the turbo interleaver address size, the address selection generator
160
discards the address. That is, the address selective generator
160
outputs the address only if it is smaller than the turbo interleaver address size. The output address is provided as an address for the interleaver memory shown in FIG.
1
.
Since many of addresses output from the address generator shown in
FIG. 2
are punctured, addresses are discontinuously generated. As a result, hardware complexity increases when configuring a real system.
The discontinuous generation of addresses makes regular addressing impossible, which implies that the clock timing of a turbo decoder cannot be kept constant in a real hardware implementation because the synchronization of the turbo decoder is based on the symbol clock signal or addressing clock signal of the interleaver.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an address generator and an address generating method in a radio communications system, which generate an address every predetermined period for turbo interleaving/deinterleaving.
It is another object of the present invention to provide an address generator and an address generating method in a radio communications system, which keeps the clock timing of a turbo decoder constant.
It is a further object of the present invention to provide an address generator and an address generating method in a radio communications system, which removes the hardware complexity in implementing a turbo decoder.
These and other objects are achieved by providing an address generator and an address generating method. According to one aspect of the present invention, the address generator generates available addresses, which are fewer than 2
k+n
and are divided into 2
k
groups each having 2
n
position addresses, without puncturing the addresses of unavailable groups and the unavailable addresses of partially unavailable groups. In the address generator, a first counter counts a plurality of clock pulses, generates a first group count value consisting of k bits and indicating one of the 2
k
groups at each clock pulse, and generates a carry after co
Kim Beong-Jo
Kim Min-Goo
Lee Young-Hwan
Dilworth & Barrese LLP
Samsung Electronics Co,. Ltd.
Vo Don N.
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