Address generation unit for a processor

Details Address generation unit for a processor Address generation unit for a processor

2008-06-03

2008-06-03

Nguyen, Than (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

C711S119000

Reexamination Certificate

active

07383419

ABSTRACT:
A processor includes a memory port for accessing a physical memory under control of an address. A processing unit executing instructions stored in the memory and/or operates on data stored in the memory. An address generation unit (“AGU”) generates address for controlling access to the memory; the AGU being associated with a plurality of N registers enabling the AGU to generate the address under control of an address generation mechanism. A memory unit is operative to save/load k of the N registers, where 2<=k<=N, triggered by one operation. To this end, the memory unit includes a concatenator for concatenating the k registers to one memory word to be written to the memory through the memory port and a splitter for separating a word read from the memory through the memory port into the k registers.

REFERENCES:
patent: 6260137 (2001-07-01), Fleck et al.
patent: 6349380 (2002-02-01), Shahidzadeh et al.
patent: 6363470 (2002-03-01), Laurenti et al.
patent: WO 9914663 (1999-03-01), None
patent: WO 0104765 (2001-01-01), None

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