Address generation unit

Details Address generation unit Address generation unit

1999-11-22

2001-11-06

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

C711S218000, C711S219000, C708S708000

Reexamination Certificate

active

06314507

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to digital signal processors and in particular to address generation units used to generate a location address in a memory for retrieving or storing M and Y operanda.
Examples of the prior art address generation units are U.S. Pat. No. 5,450,553 which disclosed a digital processor for processing digital signals, comprising an address generation unit for generating an address of an addressing mode which is used for processing the input digital signals; a setting unit for setting an initial value necessary for generating the address in advance in the address generation unit; and an instruction designating unit for designating only execution and stop of address generation to the address generation unit, wherein the address generation unit in which is set the initial value is so constructed as to perform execution and stop of address generation only by designation of the execution and stop outputted from the instruction designating means.
In a second example, Motorola Corporation of Schaumburg, Ill. disclosed in the manual for the DSP56300 core an Address Generation Unit (AGU). The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses. The AGU implements four types of arithmetic: linear, modulo, multiple wrap-around modulo and reverse-carry and operates in parallel with other chip resources to minimize address overhead.
SUMMARY OF THE INVENTION
An Address Generation Unit (AGU) for a processor, such as Digital Signal Processor, that includes a data memory addressable by X and Y coordinates and a program decoder. The AGU is connected to the data memory and the program decoder and the AGU includes two Arithmetic Logic Units (ALU) that are used to generate the addresses of the X and Y operands. Each ALU has a triplet of registers associated therewith and includes a linear path of a first DBLC adder. The first Distributed Binary Look-Ahead Carry (DBLC) adder has an A input, a B input, a carry input connected to receive a first control signal, and a summation output. The linear path further includes a by-pass connection for by passing the first DBLC adder. A multiplexer selects either the summation output or the by-pass as a linear output. Each ALU also includes a modulo path that is in parallel with the linear stage. The modulo path has a series connection of a Carry Sum Adder (CSA) and a second DBLC adder with a modulo output. A second multiplexer selects either the linear output or the modulo output as a result. The results from the first and second ALUs are converted into the addresses of the X and Y operands.
The AGU can generate the address of the X and Y operands using one of four arithmetic methods that include: a linear, a modulo, a multiple wrap around modulo and reverse carry.
The triplets of registers include a set of control registers, a set of offset registers, and a set of modifier registers. The contents of the control registers can be offset by a value stored in an offset register and can be modified by a value stored in a modifier register. Initially, there is a base address stored in the control registers. The addresses of the X and Y operands can thus be generated by one of the following arithmetic methods:
linearly incrementing the base address by the value stored in the offset register;
modulo incrementing the base address by the value stored in the offset registers plus the one's compliment of the value stored in the modifier registers;
linearly incrementing the base address by the ones compliment of the value stored in the offset register plus one;
modulo incrementing the base address by the ones compliment of the value stored in the offset registers plus one plus the one's compliment of the value stored in the modifier registers;
linearly incrementing the base address by the one's compliment of the value stored in the offset register plus one;
modulo incrementing the base address by the ones compliment of the value stored in the offset registers plus the value stored in the modifier registers plus one;
linearly incrementing the base address by the value stored in the offset register;
modulo incrementing the base address by the value stored in the offset registers plus the value stored in the modifier registers plus one;
reversing the bit order of the base address to obtain a reverse address, reversing the bit order of the offset value stored in the offset registers to obtain a reverse offset address, incrementing the reverse address by the reverse offset address to obtain a first result, and reversing the bit order of the first result to obtain a first result address; or
reversing the bit order of the base address to obtain a reverse address, reversing the bit order of the offset value stored in the offset registers to obtain a reverse offset address, obtaining the ones compliment of the reverse offset address to obtain a compliment address, incrementing the reverse address by the compliment address plus one to obtain a second result, and reversing the bit order of the second result to obtain a second result address.


REFERENCES:
patent: 5450553 (1995-09-01), Kitagaki et al.
patent: 5583806 (1996-12-01), Widigen et al.
patent: 5719803 (1998-02-01), Naffziger
patent: 5758178 (1998-05-01), Lesartre
patent: 6047364 (2000-04-01), Kolagotla et al.
patent: 6209076 (2001-03-01), Blomgren
patent: WO 95/00900 (1993-06-01), None
Motorola Corporation ofSchaumburg, Illinois,,Manual ofDSP56300 Core,Section entitled “Address Generation Unit”, pp. 4-1 through 4-12.

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