Address generation apparatus and method using a peripheral addre

Details Address generation apparatus and method using a peripheral addre Address generation apparatus and method using a peripheral addre

1997-08-13

1998-06-02

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

711218, G06F 1200

Patent

active

057616906

ABSTRACT:
Data block identification within a processor 100 may be accomplished when the processor 100 receives an interrupt while performing a main set of operational codes. Upon receiving the interrupt, the processor 100 determines whether the interrupt is of a fast interrupt type. When the interrupt if of a fast interrupt type, the processor executes the operational codes identified by the interrupt without having to flag the main set of operational codes. Upon completion of the fast interrupt, the processor 100 resumes performing the main set of operational codes. In addition to performing the fast interrupt, the processor 100 contemporaneously performs a data block identification routine. When the data block identification routine identifies a data block, the main set of operational codes is interrupted to perform a data block service routine. The processor 100 includes an address generation unit 102 and a peripheral address generation unit 104. The peripheral address generation unit 104 will provide addresses for storing data samples in a data memory 103 in response to an interrupt request when address generation unit 102 does not have an available address register 113.

REFERENCES:
patent: 4949391 (1990-08-01), Faulkerson et al.
patent: 5287193 (1994-02-01), Lin
patent: 5321806 (1994-06-01), Meinerth et al.
patent: 5339416 (1994-08-01), Nakagami et al.

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