Address generating circuit

Details Address generating circuit Address generating circuit

1999-01-27

2002-08-13

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Incrementing, decrementing, or shifting circuitry

Reexamination Certificate

active

06434686

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The invention relates to an address generating circuit for generating an access address to a memory for storing data, and more particularly to an address generating circuit suitable to read data, which was written in the memory, with its order changed.
2. Description of the Related Art
Conventionally, audio data and image data are encoded and compressed when stored or transmitted, then expanded and decoded when reproduced or received.
For example, when recording an MD (mini disc), a speech signal is converted into digital data (A/D conversion), which is then divided into three bands such as low, middle, and high (frequency bands) by a digital filter called QMF (Quadrature Mirror Filter). The obtained data is subjected to MDCT (Modified Discrete Cosine Transform) processing, quantizing processing, or the like and written on the MD. When the MD is played, the data is inversely processed by reverse quantizing, IMDCT (Inverse MDCT), inverse-filtering by IQMF (Inverse QMF), and D/A conversion.
In performing the above-described processing, a memory is required in order to store data being processed. For example, the memory temporarily stores data being sent from the preceding filter and reads it before the MDCT processing is performed.
MDCT and IMDCT process data by dividing it into 1SG (sound group) for every 11.6 msec. This 1SG corresponds to 1024 words, but MDCT and IMDCT process 1024+192 words in order to overlap slightly data across the boundary of the sound groups. Therefore, IMDCT outputs for example 1024+192 words of data for every 1SG. And, 1024 words of data is supplied to IQMR for every 1SG.
IMDCT separately outputs data of an L (left) channel and data of a R (right) channel. Specifically, for 1SG of data, data of the L channel is output, then data of the R channel is output. Meanwhile, data of the L channel and that of the R channel are alternately output to IQMF.
A capacity of 2240 words is provided for the memory by adding a capacity for writing the output data from IMDCT and a capacity for reading and used to read 1SG of data after the completion of writing. Therefore, a memory capacity therefor is 1024×2+191=2240 words.
Thus, the provision of the capacities for writing and reading for 1SG of data allows to write and read without any problem by switching a writing area and a reading area for every period of 1SG.
However, it is desirable that the memory capacity be made as small as possible. Since reading can be made without writing 1SG of data in the memory, the memory capacity may be made small by a device able to manage the memory.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an address generating circuit with a small memory capacity.
The invention relates to an address generating circuit for generating an access address to a memory for storing a predetermined amount of data comprising a counter of a predetermined number of bits and which counts prescribed clocks to determine output as an access address, wherein the position of a least significant bit (LSB) of output from the counter is counted in a state shifted by a predetermined number of bits at intervals of predetermined time, and output from the counter is determined as an address.
The invention also relates to an address generating circuit for generating a writing address to and a reading address from a memory for storing a predetermined amount of data comprising a write address counter with a predetermined number of bits and which counts a first clock and determines output as a write address; and a read address counter with a predetermined number of bits which counts a second clock and determines output as a read address, wherein the positions of least significant bits (LSB) of output from both counters is shifted by the same number of bits at intervals of predetermined time, the position of a least significant bit of output from the read address counter prior to shifting is corresponded with the shift position of the write address counter after shifting and counted by both the counters. Counting is made by both the counters in this state, and the counted outputs are determined as a write address and a read address.
The present invention sequentially writes into areas from which reading is completed. Therefore, total memory capacity can be used efficiently and a need for excessively large capacity can be eliminated.


REFERENCES:
patent: 5138501 (1992-08-01), Ii et al.
patent: 5469269 (1995-11-01), Yun
patent: 5488658 (1996-01-01), Hirashima
patent: 5842169 (1998-11-01), Sakashita

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