Address generating apparatus and motion vector detector

Details Address generating apparatus and motion vector detector Address generating apparatus and motion vector detector

2001-06-27

2003-12-09

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Slip control, misaligning, boundary alignment

C711S217000, C711S218000, C711S173000

Reexamination Certificate

active

06662288

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an address generating apparatus and a motion vector detecting apparatus and, more particularly, to an improved address generation mechanism to perform data memory access which is employed for reading/writing image data by a digital signal processor for image processing or the like, and an image data controlling apparatus which performs motion vector detection employing that mechanism.
BACKGROUND ART
In a signal processor handling image data and the like, an address generating apparatus which generates addresses of a two-dimensional rectangular area is employed as an address generating apparatus which can efficiently access a data memory
This is because, while, for example, data arranged two dimensionally such as image data should be mapped in one-dimensional address space when they are to be stored into a memory, and generally, image data are generally mapped in one-dimensional addresses in the order in which the image data are raster scanned, in a case where these data are handled as two-dimensional data, a rectangular area is often cut out to be used.
As an address generating apparatus which generalizes this kind of address generating apparatus, there is one disclosed in Japanese Published Patent Application No. Hei. 4-218847, which can access to a multidimensional area in data memory, the configuration of which is illustrated in FIG.
18
.
In
FIG. 18
, numerals
901
-
1
through
901
-N denote incremental value setting means in first through Nth scanning directions, respectively, numeral
902
denotes a first multiplexer which selects one of the outputs of the incremental value setting means in the first scanning direction
901
-
1
through the incremental value setting means in the Nth scanning direction
901
-N to output the same, numeral
903
denotes a start address setting means which sets an start address, numerals
904
-
1
through
904
-N denote first through Nth cumulative registers which correspond to the first through Nth scanning directions, respectively, numeral
905
denotes a second multiplexer which selects one of the outputs of the first cumulative register
904
-
1
through Nth cumulative register
904
-N to output the same, numeral
906
denotes an adder which adds the output of the first multiplexer
902
and the output of the second multiplexer
905
, numeral
907
denotes a third multiplexer which selects one of the outputs of the adder
906
and the start address setting means
903
to output the same, numerals
908
-
1
through
908
-N denote data number setting means in the first scanning direction through the Nth scanning direction, respectively, and numeral
909
denotes a control circuit which generates a control signal based on set values of the data number setting means
908
-
1
in the first scanning direction through the data setting means
908
-N in the Nth scanning direction.
The multidimensional address generating apparatus configured as described above has the output of the first cumulative register
904
-
1
as an output address.
FIG. 19
is one having simplified the multidimensional address generating apparatus in
FIG. 18
so that it can generate a two-dimensional address, and hereinafter, the operation of the multidimensional address generating apparatus in
FIG. 18
will be described as referring to a case where a two-dimensional address is generated by this conventional two-dimensional address generating apparatus, for simplification.
First, suppose that a rectangular area of arbitrary P
1
×P
2
(P
1
and P
2
are natural numbers such as 16 and 16, for example) is an access object. Initially, at 0th cycle, start address data SA is set to the first cumulative register
904
-
1
and the second cumulative register
904
-
2
as an initial value by a start address data setting device
903
.
At a subsequent first cycle, data of the first cumulative register
904
-
1
and incremental data DX in the first scanning direction (direction X) are added by the adder
906
and the addition result is written into the first cumulative register
904
-
1
, so as to generate an address immediately after the initial value. The writing is not performed to the second cumulative register
904
-
2
. Subsequently, the same operation as that at the first cycle is performed from second cycle to P
1
−1th cycle to continue writing.
Next, at P
1
th cycle, data of the second cumulative register
904
-
2
and incremental data DY in the second scanning direction (direction Y) are added by the adder
906
and the addition result is written into both of the first cumulative register
904
-
1
and the second cumulative register
904
-
2
.
Similarly, every other cycle from P
1
+1th cycle to 2P
1
−1th cycle, . . . , from (P
2
−1) P
1
+1th cycle to P
2
·P
1
−1th cycle, a control is performed so that the data of the first cumulative register
904
-
1
and the incremental data DX in the first scanning direction are added by the adder
906
and the result is written into the first cumulative register
904
-
1
, and at every P
1
cycle of P
1
th cycle, 2P
1
th cycle, . . . , (P
2
−1) P
1
th cycle, a control is performed so that the data of the second cumulative register
904
-
2
and the incremental data DY in the second scanning direction are added and the result is written into the first cumulative register
904
-
1
and the second cumulative register
904
-
2
, thereby outputting a value of the first cumulative register
904
-
1
obtained as a result of carrying out the 0th cycle to the P
2
·P
1
−1th cycle as an address.
A data flow due to such operation will be described in FIG.
20
. An initial address of a subsequent line is calculated employing an initial address of a previous row or column stored in the second cumulative register
904
-
2
as shown in FIG.
20
.
An example of the control circuit
909
in
FIG. 19
will be described in FIG.
21
. In
FIG. 21
, numeral
909
-
1
denotes a first counter, an initial value of which is P
1
, and which repeats the operation of starting a count from 1 to sequentially increment to P
1
according to a clock, numeral
909
-
3
denotes a second counter, an initial value of which is P
2
, and which repeats the operation of starting a count from 1 to sequentially increment to P
2
according to a clock, numeral
909
-
2
denotes a data P
1
, numeral
909
-
4
denotes a data P
2
, numeral
909
-
11
denotes a data P
1
-
1
, numerals
909
-
5
and
909
-
8
denote AND circuits, numerals
909
-
6
,
909
-
7
, and
909
-
12
denote comparators which compare two data to output
1
when they match and to output
0
when they do not match, numerals
909
-
9
,
909
-
10
, and
909
-
13
denote D flipflops, numeral
909
-
14
denotes a first clock, numeral
909
-
15
denotes a second clock, numeral
909
-
16
denotes a control signal, and numeral
909
-
17
denotes an END signal.
The control circuit in
FIG. 21
operates at a timing in FIG.
20
. The control signal
909
-
16
is employed as a first control signal
29
-
1
and a second control signal
29
-
2
in figure
19
, the first clock
909
-
14
is employed as a writing signal
29
-
4
, and the second clock
909
-
15
is employed as a second writing signal
29
-
5
, thereby performing a control following a timing chart in FIG.
22
.
A third control signal
29
-
3
of a third multiplexer
917
in
FIG. 19
performs a control so that a start address data of the start address data setting device
903
is selected at the activation of a two-dimensional address generating apparatus (at a 0th cycle), while an output address of the adder
906
is selected at other cycles.
An example of a state where actual image data are accessed will be described in FIG.
23
. FIG.
23
(
a
) is a schematic diagram illustrating an access in a lateral direction and FIG.
23
(
b
) is a schematic diagram illustrating an access in a longitudinal direction.
First, the operation when an access is performed in a lateral direction will be described with reference to FIG.
23
(
a
). Numeral
61
denotes a whole image

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