Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-08-04
2001-08-07
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S236000
Reexamination Certificate
active
06272065
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a random access memory device, and more particularly to an address generating and decoding circuit for use in the burst-type random access memory that has a double data rate, and to an address generating method thereof.
BACKGROUND OF THE INVENTION
Video random access memory (RAM), synchronous RAM and burst RAM require generating a sequence of internally generated addresses (referred to as “an address burst” or “an address sequence”) for high-speed access thereof. In general, a start address (or initial address) of particular address burst is supplied from the exterior (for example, host computer or processor). Then, when next clock signals reach an address generator, next addresses of the particular address burst are sequentially generated in an address generator during a burst period.
Address generator technologies for performing such a function are disclosed in U.S. Pat. No. 5,596,616, entitled “Burst Address Sequence Generator For Addressing Static Random-Access-Memory Devices”, U.S. Pat. No. 5,708,688, entitled “High Speed Programmable Burst Address Generation Circuit”, and U.S. Pat. No. 5,452,261, entitled “Serial Address Generator For Burst Memory”, which are hereby incorporated by reference.
The above mentioned references are used in random access memory devices each of which has a single data rate scheme. This means that only one data is inputted/outputted to/from the memory devices during one clock cycle. Although high-speed access operation can be performed by implementing a burst mode in each random accesses memory device, users continue to require more rapid access operation.
In order to satisfy such a requirement, the double data rate scheme (hereinafter, referred to as “DDR scheme”) has been proposed, in which at least two data is inputted/outputted to/from the memory device during one clock cycle (or a system clock cycle). The burst-type random access memory device with such a DDR scheme can have about twice access speed, as compared with that having the single data rate scheme.
To input/output two data during one clock cycle in the burst-type random access memory device with the DDR scheme, addresses are required to be generated during a first logic state period of the clock cycle and during a second logic state period thereof, respectively. This requires two address generating circuits, one for generating an address for the first logic state period (hereinafter, referred to as a first half period), and the other for generating an address for the second logic state period (hereinafter, referred to as a second half period).
Referring to
FIG. 1
, there is illustrated A block diagram of a conventional address generating and decoding circuit for use in a burst-type random access memory device with the DDR scheme. An address buffer
10
receives an externally applied a multi-bit input address An, which is used as the start (or initial) address. An address sequencer
12
(typically a counter) receives the start address from the address buffer
10
, and then generates a sequence of addresses for the first half period of each clock cycle in accordance with a burst mode. As is known, this burst mode can be a sequential mode or an interleaved mode. The address sequencer
12
has been disclosed in U.S. Pat. No. 5,481,581, entitled “Programmable binary/interleave sequence counter”, and U.S. Pat. No. 5,594,765, entitled “Interleaved and sequential counter”, which are hereby incorporated by reference.
The start address An from the address buffer
10
is supplied to a first and a second decoder
14
and
18
, together with the addresses generated by the address sequencer
12
. The first decoder
14
decodes the address for the first half period of each clock cycle, which is provided from the address buffer
10
, and from the address sequencer
12
, respectively. The second decoder
18
generates an address for the second half period of each clock cycle in response to the address from the address buffer
10
or from the address sequencer
12
. A detailed circuit diagram of the second decoder
18
is illustrated in FIG.
2
.
As illustrated in
FIG. 2
, the conventional second decoder
18
used as an address generator is embodied only by the combination of logic gate circuits. In particular, instead of an address generation structure, the second decoder
18
is configured so as to have all practicable cases of addresses for the second half period of each clock cycle by using burst length (for example, BL
4
and BL
8
) and burst mode (an interleaved or a sequential mode) information, and address signals from the address buffer
10
or from the address sequencer
12
.
According to the conventional address generating and decoding circuit structure, as more types of burst length are provided in the burst-type random access memory device with the DDR scheme, the number of the logic gate circuits and fan-in of the respective logic gate circuits are increased more and more. This is because generating an address for the second half period of each clock cycle requires combining of the addresses in all permutations for the second half period according to the burst length and the burst mode. Therefore, the access speed of the burst-type random access memory device with the DDR scheme is decreased, and the conventional second decoder
18
used as an address generator may be too complicated to be implemented in a semiconductor chip. And the required number increases geometrically for longer burst lengths.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved address generating and decoding circuit for use in a burst-type random access memory device with a double data rate scheme.
In order to attain the above object, according to an aspect of the present invention, there is provided a burst-type random access memory device which has a memory cell array for storing data and has a double data rate scheme, in which at least two data is inputted/outputted to/from the memory device during a clock cycle. In the burst-type random access memory device, an address buffer, a first address generator and a second address generator are provided. The address buffer receives an externally applied initial address. The first address generator sequentially generates first addresses in response to the initial address from the address buffer, wherein the first addresses correspond to a first half period of the clock cycle during a burst mode of operation, respectively. And, the second address generator receives the first addresses and generates second addresses in accordance with burst information signals each indicative of a burst length and a type of the burst mode of operation, wherein the second addresses correspond to a second half period of the clock cycle during the burst mode of operation, respectively.
In the device according to the invention, the second address generator comprises an address incrementor for receiving remaining address bits of a first address except a least significant bit and incrementing a value of the remaining address bits by one to output the incremented address bits as a third address, wherein the remaining address bits correspond to the incremented address bits, respectively; a select signal generator for generating select signals in response to the burst information signals and the least significant bit of the first address, wherein the select signals correspond to the incremented address bits, respectively; and a selector for receiving the remaining address bits and the incremented address bits, wherein the selector chooses one of corresponding address bits of the first and the third address in response to the select signals and outputs the chosen address bits as a second address.
According to another aspect of this invention, there is provided a method of generating an address for a burst mode of operation in a burst-type random access memory device having a double data rate scheme in which at least two data is inputted/outputted to/from the random access memory device during
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Zarabian A.
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