Address encoding method and address decoding circuit therefor

Details Address encoding method and address decoding circuit therefor Address encoding method and address decoding circuit therefor

1992-09-01

1997-12-09

Bowler, Alyssa H.

Communications: electrical

Continuously variable indicating

With meter reading

H03K 300

Patent

active

056964986

ABSTRACT:
An address encoding method and an address decoding circuit therefor is disclosed. In the address encoding method, a part of the outputs of address latches are made to designate circuits to be controlled, and the rest of the outputs are made to designate the relevant addresses of the circuits to be controlled. Based on this method, the constitution of the decoding circuit becomes simple.

REFERENCES:
patent: 3903499 (1975-09-01), Oliver
patent: 4570154 (1986-02-01), Kinghorn et al.
patent: 4571587 (1986-02-01), Higginbotham et al.
patent: 4716410 (1987-12-01), Nozaki
patent: 5208781 (1993-05-01), Matsushima
IBM, Technical Disclosure Bulletin vol. 32 No. 11, Apr. 1990, USA, "Advanced Synchronous Data Link Control".
Texas Instruments, The TTL DataBook, Second Edition; 1976; USA; pp. 7-157 to 7-158g "Data Selectors/Multiplexers"; pp. 7-165 to 7-166, Dual 4-Line-to-1-Line Data Selectors/Multiplexers; pp. 7-175 to 7-176, Dual 2-Line-to-4-Line Decoders/Demultiplexers; pp. 7-181 to 7-183, Quadruple 2-Line-to-1 Line Data Selectors/Multiplexers.
Texas Instruments, "Supplement to The TTL Data Book", Second Edition; 1981; USA; pp. 19-22, 3-Line-to 8-Line Decoders/Demultiplexers with Address Latches.

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