Address dependent retry system to program the retry latency of a

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

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710 4, 710 5, 710 39, 710 45, 710110, 710112, 113117, 113118, 113105, 113125, 113126, 113241, G06F 1300

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06081859&

ABSTRACT:
The present invention comprises a smart retry system for a PCI (peripheral component interconnect) agent in a PCI bus system. The system of the present invention includes an initiator PCI agent, a retry identification register, and a completion counter. The initiator PCI agent is adapted to couple to a PCI bus and communicate with a target PCI agent via the PCI bus by initiating a data transaction. The retry identification register is coupled to the initiator PCI agent. The retry identification register is adapted to store a target address and a transaction type corresponding to the target PCI agent when the target PCI agent issues a retry to the initiator PCI agent. The completion counter is coupled to the initiator PCI agent and is adapted to measure a latency period of the target PCI agent. The completion counter couples the latency period to the initiator PCI agent such that the initiator PCI agent efficiently completes a subsequent access corresponding to the target address and to the transaction type by initiating the subsequent access at the expiration of the latency period.

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patent: 5623694 (1997-04-01), Arimilli et al.
patent: 5717872 (1998-02-01), Whittaker
patent: 5771235 (1998-06-01), Tang et al.
patent: 5884052 (1999-03-01), Chambers et al.

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