Address decoding systems and methods

Details Address decoding systems and methods Address decoding systems and methods

2008-03-11

2008-03-11

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080, C365S194000, C365S233100

Reexamination Certificate

active

07342846

ABSTRACT:
Systems and methods provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signal and provides a registered address signal. The registered address signal provides at least a true and a complement signal, with the true and complement signal set to approximately the same logical value upon assertion of the reset signal. An address pre-decoder, coupled to the address register, at least partially decodes the registered address signal to provide a pre-decoded output signal. A wordline driver, coupled to the address pre-decoder, receives a wordline enable signal and the pre-decoded output signal and provides a wordline signal based on the pre-decoded output signal upon assertion of the wordline enable signal.

REFERENCES:
patent: 4160291 (1979-07-01), Smith et al.
patent: 5022010 (1991-06-01), Chan
patent: 5068881 (1991-11-01), Dervisoglu et al.
patent: 6198650 (2001-03-01), Suh
patent: 6998878 (2006-02-01), Kanetani et al.

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