Address decoding . . . semiconductor memory

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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Details

36523002, 36523008, 365233, G11C 800

Patent

active

058154590

ABSTRACT:
Methods and apparatus are disclosed for receiving and decoding address information applied to a synchronous semiconductor memory device. Separate read address and write address decoders and latches are provided for decoding the address without waiting for a determination as to whether a read cycle or a write cycle is undertaken, thereby reducing the decoding delay and thereby increasing the speed of such a device in operation.

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patent: 5493536 (1996-02-01), Aoki
patent: 5513139 (1996-04-01), Butler
patent: 5596540 (1997-01-01), Diem et al.

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