Address decoding circuit

Details Address decoding circuit Address decoding circuit

1998-06-23

2000-08-22

Tokar, Michael

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326106, G11C 800

Patent

active

061078379

ABSTRACT:
A decoding circuit decodes address signals of 7-bit so as to select one of 128 decoded signals preliminarily set to selective condition and keeps its selective condition. Then the decoding circuit switches the other decoded signals except the selected decoded signal from the selective condition to non-selective condition. A buffer circuit detects that the decoded signals different from the decoded signal kept in the selective condition have been switches from the selective condition to the non-selective condition by receiving the 128 decoded signals from the decoding circuit. Then the buffer circuit selects an output selective signal corresponding to the decoded signal in the selective condition, out of the 128 output selective signals corresponding to the 128 decoded signals, and makes the output selective signal in the selective condition.

REFERENCES:
patent: 5532971 (1996-07-01), Tanaka et al.

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