Address decoder

Details Address decoder Address decoder

1996-09-26

1999-04-06

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

326105, G11C 800

Patent

active

058927263

ABSTRACT:
An address decoder with low power consumption of feedthrough current, leakage current, etc. Address bits AY0.sub.0 -AY0.sub.7 are respectively supplied to n-type gate terminals of CMOS transfer gates C.sub.0 -C.sub.7 and the gate terminals of PMOS transistors P.sub.0 -P.sub.7. Inverted address bits AY0.sub.0- -AY0.sub.7- are supplied to p-type gate terminals of the CMOS transfer gates C.sub.0 -C.sub.7. Enable signals AY3.sub.p, AY6.sub.q are respectively input to both input terminals of a NAND circuit 10. The output terminals of NAND circuit 10 are connected to the input terminals of CMOS transfer gates C.sub.0 -C.sub.7. The output terminals of CMOS transfer gates C.sub.0 -C.sub.7 are connected to the input terminals of the drivers D.sub.0 -D.sub.7 and the drain terminals of the PMOS transistors P.sub.0 -P.sub.7 via a node F.sub.0 -F.sub.7. The source terminals of PMOS transistors P.sub.0 -P.sub.7 are connected to a power supply voltage V.sub.cc, for example of 3.3 V. The output terminals of drivers D.sub.0 -D.sub.7 are connected to Y-address lines YS.sub.0 -YS.sub.7.

REFERENCES:
patent: 5365489 (1994-11-01), Jeong
patent: 5469391 (1995-11-01), Haraguchi
patent: 5528177 (1996-06-01), SridhAr et al.
patent: 5539698 (1996-07-01), Suzuki

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