Address decoder which variably selects multiple rows and/or colu

Details Address decoder which variably selects multiple rows and/or colu Address decoder which variably selects multiple rows and/or colu

1992-04-13

1994-02-22

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 3652385, G11C 800

Patent

active

052894290

ABSTRACT:
An address decoder comprising a match signal generating circuit responsive to an inputted address signal and an address mask signal to mask any given bits of the inputted address signal, and an address selection signal generating circuit responsive to signals outputted from the match signal generating circuit, for generating a selection signal of a plurality of addresses which have corresponding bit values except for the masked bits. The address decoder can be used as a row address decoder or column address decoder of the semiconductor memory device for selecting a plurality of addresses simultaneously.

REFERENCES:
patent: 4636986 (1987-01-01), Pinkham
patent: 4691295 (1987-09-01), Erwin et al.
patent: 4807189 (1989-02-01), Pinkham et al.
patent: 4926386 (1990-05-01), Park
patent: 4962486 (1990-10-01), Masuda et al.
patent: 5134589 (1992-07-01), Hamano

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