Master slice integrated circuit having a memory region

Details Master slice integrated circuit having a memory region Master slice integrated circuit having a memory region

1988-03-08

1989-07-18

Hecker, Stuart N.

Static information storage and retrieval

Interconnection arrangements

36523004, 364489, 357 40, G11C 700

Patent

active

048499323

ABSTRACT:
A gate array chip (33) has an array (41) of strip-shaped active areas (18) formed on a semiconductor substrate (40). Wiring-dedicated areas (34), each having capacity for two to four wires, are provided between respective adjacent pairs of the active areas (18). In a logic circuit region, one or more active areas (18) are employed as wiring areas. In memory blocks, wiring is performed by employing only the wiring-dedicated areas (34). A master slice integrated circuit manufactured from the gate array chip (33) has a high degree of integration and high operating speed.

REFERENCES:
patent: 4780846 (1988-10-01), Tanabe et al.
patent: 4791609 (1988-12-01), Ito
Takashi Saigo et al., "A Triple-Level Wired 24K Gate CMOS Gate Array", pp. 122-123, ISSCC 85 Proceedings (1985).

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